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Find edges of a 20MHz clock generated with the clk_wiz (CDC) problem
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2
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55
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October 6, 2025
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Cannot flash Au
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32
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317
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October 1, 2025
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Community Feedback
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13
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304
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September 25, 2025
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Cu V2 and iceprog
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8
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135
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September 23, 2025
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DDR3 different clock domains
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5
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85
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September 18, 2025
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Sense of ack_write in I2C module seems backwards
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1
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73
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September 18, 2025
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Servos safe to directly connect to Au V1
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2
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62
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September 18, 2025
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PT v2 DDR chip part number
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2
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51
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September 18, 2025
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Issues getting started with Alchitry Labs IDE 2.0.39
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2
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87
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September 18, 2025
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Component part numbers
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17
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255
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September 11, 2025
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What happened to A1, B1, A2 , B2 , A7 , B7 etc
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1
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71
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August 15, 2025
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100 ohm differential pairs
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5
|
165
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August 14, 2025
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Is it possible to use Vivado to write HDL and program the V2 boards directly?
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3
|
143
|
August 9, 2025
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SPI flash swaping on Au V2
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10
|
185
|
August 3, 2025
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Servo on Au V2 no signal out
|
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2
|
49
|
August 1, 2025
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Code errors with https://alchitry.com/tutorials/io-element/
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2
|
66
|
July 17, 2025
|
|
Vivado 2025 Licensing Differences
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2
|
402
|
July 14, 2025
|
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Compatibily of Pt first batch with element boards
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1
|
55
|
July 9, 2025
|
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Yosys Pipeline Error with 2.0.37
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3
|
47
|
July 7, 2025
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Lets run vivado with my Au version1
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1
|
99
|
July 7, 2025
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Au V2 with Fn V2 No board detected
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3
|
79
|
July 3, 2025
|
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Au V2 having Issues with Vivado
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3
|
131
|
June 27, 2025
|
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Ubuntu issues with alchitryloader and serial port
|
|
15
|
119
|
June 10, 2025
|
|
Alchitry Cu V2 Connection List
|
|
6
|
205
|
June 7, 2025
|
|
NeoRV32 on AU board
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|
18
|
277
|
June 6, 2025
|
|
"Bin file (*\alchirty_top.bin) could not be found. Version 2.0.34 on Windows 11 HP Laptop
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9
|
53
|
June 1, 2025
|
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Possible UI improvements
|
|
2
|
69
|
May 19, 2025
|
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Hd signal confusion
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4
|
91
|
May 18, 2025
|
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Powering boards from external supply
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|
1
|
78
|
May 18, 2025
|
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Au V2 vivado only development
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|
8
|
278
|
May 17, 2025
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