Alchitry V2 Planning
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100
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555
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February 16, 2025
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Issues with I2C reading eeprom 24AA32A
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3
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17
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February 14, 2025
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Alchitry Labs freezes
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7
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69
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February 12, 2025
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Vivado legacy instalation
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1
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20
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February 11, 2025
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AU SPI question (slave mode)
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44
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151
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February 7, 2025
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Do test benches work with Verilog modules?
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4
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23
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February 7, 2025
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Does the serial terminal work with Cu V2?
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7
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38
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February 5, 2025
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CLK Generation from FPGA
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6
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67
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February 5, 2025
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Alchitry Cu External Clock
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3
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34
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February 5, 2025
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Arch Linux - ChacyOS support for Alchitry Labs V2 2.0.24
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2
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36
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January 27, 2025
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IDE Hangs for large builds
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3
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31
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January 27, 2025
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Contact to Alchitry shop
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1
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23
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January 26, 2025
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Yosys error: can't guess frontend for input file
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9
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199
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January 25, 2025
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New Project fails in Ubuntu/kUbuntu with Plasma Desktop
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4
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44
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January 24, 2025
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Alchitry Pt board
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1
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49
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January 23, 2025
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Vivado MIG generator. Rules OK?
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3
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17
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January 23, 2025
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Unable top create new project
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2
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40
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January 20, 2025
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Help/Question: Need 88 LVDS Pairs for Piano Project
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9
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64
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January 20, 2025
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Alchitry Au board interfacing issue
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3
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59
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January 13, 2025
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No Devices Detected with Vivado Hardware Manager
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26
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824
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January 12, 2025
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Finding a connectors for Alchitry Au Board
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1
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26
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January 10, 2025
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Button problems
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5
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45
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December 20, 2024
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Labs V2 suggestions
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14
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106
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December 13, 2024
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Au+ Bitstream settings for Quad Mode?
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11
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65
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December 12, 2024
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Alchitry Hd - design recomendation
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1
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28
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December 11, 2024
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Verilog top module in V2
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23
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145
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December 10, 2024
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Cannot flash Au
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27
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89
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December 9, 2024
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V2 Au vs Pt Top pinout differences
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1
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30
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December 9, 2024
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Alchitry Ft (FT600) example project
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4
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298
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December 7, 2024
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Pinouts side-by-side for AU, IO and FT
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0
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43
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December 4, 2024
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