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About the Help Request category
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0
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76
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March 15, 2024
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DDR3 different clock domains
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4
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19
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August 21, 2025
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100 ohm differential pairs
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5
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100
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August 14, 2025
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PT v2 DDR chip part number
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1
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20
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August 10, 2025
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Servo on Au V2 no signal out
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2
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37
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August 1, 2025
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Yosys Pipeline Error with 2.0.37
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3
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29
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July 7, 2025
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Au V2 with Fn V2 No board detected
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3
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61
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July 3, 2025
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Au V2 having Issues with Vivado
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3
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80
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June 27, 2025
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Ubuntu issues with alchitryloader and serial port
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15
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72
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June 10, 2025
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Alchitry Cu V2 Connection List
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6
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95
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June 7, 2025
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Hd signal confusion
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4
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73
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May 18, 2025
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Trouble instantiating Ft module
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3
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61
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May 10, 2025
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Flashing the CU V2 without Alchitry Labs
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3
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101
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May 7, 2025
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Trouble monitoring serial transmission on Debian
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3
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55
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April 28, 2025
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Issues with IO Board Template
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4
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93
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April 28, 2025
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no boot for alchitry au
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4
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63
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April 20, 2025
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Alchitry Au mechanical placement of connectors
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7
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99
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April 19, 2025
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Cu + Ft "Unknown port name" and Yosys Failures (V2)
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2
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37
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April 18, 2025
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Moving Projects from Lab1 to Labs2
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14
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114
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April 17, 2025
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BR V2 board pinout diagram
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0
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48
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April 16, 2025
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Error with counter component in Labs v2
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3
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71
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April 16, 2025
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Supply via USBC
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1
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34
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April 16, 2025
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Alchitry HD Demos?
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2
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74
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April 16, 2025
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How to connect 7 Segment display with Alchitry Au through breadboard?
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3
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77
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April 8, 2025
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Labs 2 Error Message
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4
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55
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March 28, 2025
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Vivado Error Using Labs 2!
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7
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90
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March 21, 2025
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Does bin_to_dec.luc handle negative numbers?
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1
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18
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March 20, 2025
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How to power GPIO pins on the Alchitry Br
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2
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74
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March 11, 2025
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Lucid V2 test bench help
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3
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60
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March 6, 2025
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Alchitry Cu External Clock
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4
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72
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February 27, 2025
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