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Community Feedback
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11
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185
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August 25, 2025
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DDR3 different clock domains
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4
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34
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August 21, 2025
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Sense of ack_write in I2C module seems backwards
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0
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29
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August 18, 2025
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What happened to A1, B1, A2 , B2 , A7 , B7 etc
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1
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36
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August 15, 2025
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100 ohm differential pairs
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5
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105
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August 14, 2025
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V2 Shield Template
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8
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170
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August 11, 2025
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Servos safe to directly connect to Au V1
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1
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34
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August 10, 2025
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PT v2 DDR chip part number
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1
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22
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August 10, 2025
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Is it possible to use Vivado to write HDL and program the V2 boards directly?
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3
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59
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August 9, 2025
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Issues getting started with Alchitry Labs IDE 2.0.39
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1
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40
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August 9, 2025
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Component part numbers
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14
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201
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August 5, 2025
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SPI flash swaping on Au V2
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10
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144
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August 3, 2025
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Servo on Au V2 no signal out
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2
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39
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August 1, 2025
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Code errors with https://alchitry.com/tutorials/io-element/
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2
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57
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July 17, 2025
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Vivado 2025 Licensing Differences
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2
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116
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July 14, 2025
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Compatibily of Pt first batch with element boards
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1
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49
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July 9, 2025
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Yosys Pipeline Error with 2.0.37
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3
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31
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July 7, 2025
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Lets run vivado with my Au version1
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1
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67
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July 7, 2025
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Au V2 with Fn V2 No board detected
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3
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64
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July 3, 2025
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Au V2 having Issues with Vivado
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3
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84
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June 27, 2025
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Book on Designing and Building a CPU
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3
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126
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June 15, 2025
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Ubuntu issues with alchitryloader and serial port
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15
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72
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June 10, 2025
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Alchitry Cu V2 Connection List
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6
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97
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June 7, 2025
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NeoRV32 on AU board
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18
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136
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June 6, 2025
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"Bin file (*\alchirty_top.bin) could not be found. Version 2.0.34 on Windows 11 HP Laptop
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9
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37
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June 1, 2025
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Possible UI improvements
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2
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58
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May 19, 2025
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Hd signal confusion
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4
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75
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May 18, 2025
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Powering boards from external supply
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1
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53
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May 18, 2025
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Au V2 vivado only development
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8
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189
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May 17, 2025
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Alchitry Au V2 Alchitry Loader doesn't see board
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3
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46
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May 17, 2025
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