100 ohm differential pairs

Help Request
1

Hi, I’d like some clarification on the Au V2 board. The specification says, “44 pins are routed as 100 ohm differential pairs (includes 20 triple voltage pins)” and “All pairs can be used as LVDS_25 inputs except three pairs on bank B”.

My question is, are the traces routed such that you don’t need a 100 ohm resistor to use LVDS_25 as an input? Or are you saying that the transmission line is matched to reduce reflections and an external 100 ohm resistor is required if i’m using a pair from the 3.3V bank?

Thanks

2

There is no external termination on any pins, so if you’re using LVDS_25 inputs on banks with a VCCO other than 2.5V, you need an external 100 ohm termination resistor placed as close to the connector as possible.

If you set the tri-voltage pins to 2.5V, then you can enable internal termination on LVDS_25 inputs for those pins.

The 100 ohm diff pair routing just means they have controlled impedance for signal integrity. It doesn’t actually matter that much since the distances are so short though. The other pairs should work just fine.

3

Got it. I kinda figured that was what it was referring to. I need ~10 lvds pairs set as inputs and ~10 lvds pairs set as outputs. I’m going to gobble most of the trivoltage pairs up with my outputs, so I’ll just have to use external 100 ohm resistors with my inouts. Hopefully placing them at the Br wide board is close enough :grimacing:

4

You may run into signal integrity issues connecting LVDS signals through the Br but it all depends on the speeds of the signals. Signals on the Br boards are not routed as differential pairs.

5

One more follow-up. In the features it mentions 20 are LVDS_25 output capable. Digging in a bit more, it looks like 18 are capable. If i understand correctly, Bank 34 is partially bonded and doesnt have a complimentary L10N.

Is that true or can it be used with IO_0_34 as the N in the pair?

6

You are correct and the description was wrong.

I just updated it to read

20 are triple voltage (3.3V, 2.5V, or 1.8V) of which 18 are LVDS_25 capable

I think I got tripped up and was looking at the clock pins from bank 14 grouped with them when I initially wrote it.