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Base Vivado project for Au+: compatibility
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1
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82
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April 15, 2022
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Always block
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1
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63
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April 15, 2022
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Troubles with CU setup
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3
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88
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April 15, 2022
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JTAG and QSPI Flash on Alchitry Au
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2
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90
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April 12, 2022
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Could not detect an Au!
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7
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95
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March 17, 2022
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URL typo error in the Alchitry Tutorials (Background) section
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1
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39
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March 17, 2022
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iceprog - Can't find iCE FTDI USB device with Alchitry CU
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0
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42
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March 3, 2022
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Moving data into a case statement
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3
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55
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February 28, 2022
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Cloning a project
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2
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39
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February 26, 2022
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Passing variables into case statements
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0
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33
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February 20, 2022
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Dead LED in display :(
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4
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44
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January 31, 2022
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Not really aimed at FPGA but…
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2
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23
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January 27, 2022
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Shields for the SparkFun DEV-17514 Alchitry Au+ Development Board
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1
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44
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January 27, 2022
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CORE Generator fails to generate core
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0
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29
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January 26, 2022
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SRAM 16 Mbit (2M x 8) 10ns board
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7
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44
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January 23, 2022
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Au + Board IP's
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2
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40
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January 22, 2022
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New to Lucid and Alchitry but...
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3
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59
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January 21, 2022
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FPGA configuration in SPI slave mode
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1
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36
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January 20, 2022
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Using Lucid for other than Demo/Tutorial designs
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1
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35
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January 20, 2022
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Verilog example for Serial data transfer on Au
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2
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69
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January 17, 2022
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AU Plus UART Capability
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2
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32
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January 12, 2022
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HDMI Error - tmds_encoder.luc bug?
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1
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27
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January 11, 2022
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Connecting multiple FPGAs?
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2
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38
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January 11, 2022
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MicroBlaze & Au Plus
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1
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40
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January 11, 2022
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routing DDR3 fails with invalid clock parameters
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3
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122
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January 2, 2022
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Au plus and DDR3 Tutorial
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6
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73
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December 28, 2021
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ADC and HDMI clock synchornization
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0
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25
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December 27, 2021
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Alchitry a dying project?
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2
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45
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December 26, 2021
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Serial Port Monitor is not Windows compatible
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0
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25
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December 24, 2021
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Cannot Build Cu Hello World with IceStorm
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0
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36
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December 17, 2021
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