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FT FT600 only works when on top?
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22
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366
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November 18, 2025
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Regulator failure on 1V8 from ADP5052ACPZ-R7 on Pt board?
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4
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89
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November 18, 2025
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Alchitry Labs: Load Flash and Load RAM remain unavailable after setup
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1
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42
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November 18, 2025
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Schematic issue on Pt (34_L21N connected to 34_L15_N)?
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2
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82
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November 14, 2025
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Using the usb as serial port
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3
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83
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November 14, 2025
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Pt bottom side to Br breakout board pinout issue
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10
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113
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November 5, 2025
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How can i use the divider_generator from vivado ip catalog
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1
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57
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November 4, 2025
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PCIe connector board
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1
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69
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November 4, 2025
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V2 Power/Control JTAG
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1
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62
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November 4, 2025
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V2 Shield Template
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10
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300
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October 31, 2025
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Thought on Litex support for the v2 boards
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1
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76
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October 28, 2025
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PCF for Cu V2 with IO V2
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2
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126
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October 18, 2025
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No Devices Detected with Vivado Hardware Manager
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27
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2469
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October 17, 2025
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Find edges of a 20MHz clock generated with the clk_wiz (CDC) problem
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2
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62
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October 6, 2025
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Cannot flash Au
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32
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325
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October 1, 2025
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Community Feedback
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13
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316
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September 25, 2025
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DDR3 different clock domains
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5
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96
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September 18, 2025
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Sense of ack_write in I2C module seems backwards
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1
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75
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September 18, 2025
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Servos safe to directly connect to Au V1
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2
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64
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September 18, 2025
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PT v2 DDR chip part number
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2
|
52
|
September 18, 2025
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Issues getting started with Alchitry Labs IDE 2.0.39
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2
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90
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September 18, 2025
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Component part numbers
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17
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258
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September 11, 2025
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What happened to A1, B1, A2 , B2 , A7 , B7 etc
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1
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81
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August 15, 2025
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100 ohm differential pairs
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5
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192
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August 14, 2025
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Is it possible to use Vivado to write HDL and program the V2 boards directly?
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3
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171
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August 9, 2025
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Servo on Au V2 no signal out
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2
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51
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August 1, 2025
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Code errors with https://alchitry.com/tutorials/io-element/
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2
|
67
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July 17, 2025
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|
Vivado 2025 Licensing Differences
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2
|
479
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July 14, 2025
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Compatibily of Pt first batch with element boards
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1
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57
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July 9, 2025
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Yosys Pipeline Error with 2.0.37
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3
|
48
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July 7, 2025
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