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How to modify data using an externally uploaded file
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6
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61
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April 28, 2025
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Alchitry V2 Planning
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118
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1185
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April 24, 2025
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no boot for alchitry au
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4
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62
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April 20, 2025
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Alchitry Au mechanical placement of connectors
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7
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88
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April 19, 2025
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Cu + Ft "Unknown port name" and Yosys Failures (V2)
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2
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34
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April 18, 2025
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Moving Projects from Lab1 to Labs2
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14
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112
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April 17, 2025
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BR V2 board pinout diagram
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0
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41
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April 16, 2025
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Error with counter component in Labs v2
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3
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70
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April 16, 2025
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Supply via USBC
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1
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29
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April 16, 2025
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Alchitry HD Demos?
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2
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63
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April 16, 2025
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Stacking boards
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5
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121
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April 12, 2025
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LED Blinking: Troubleshooting Help Needed!
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5
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60
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April 11, 2025
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NRF24L01 safe for AU V1
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4
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40
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April 8, 2025
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How to connect 7 Segment display with Alchitry Au through breadboard?
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3
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70
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April 8, 2025
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The possible defect on Au ver1 bank 34
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2
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50
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April 8, 2025
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Inaccessible pins on breakout board? on 'c' bank?
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5
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53
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April 1, 2025
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New Alchitry Cu on macOS
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12
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161
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March 29, 2025
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Labs 2 Error Message
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4
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54
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March 28, 2025
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Alchitry Labs freezes
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9
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122
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March 28, 2025
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Alchitry Au v2 oscillator tolerance
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3
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47
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March 28, 2025
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Vivado Error Using Labs 2!
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7
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80
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March 21, 2025
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Labs V2 suggestions
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18
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217
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March 21, 2025
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Does bin_to_dec.luc handle negative numbers?
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1
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16
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March 20, 2025
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Au+ Standard Vivado Project
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2
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408
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June 14, 2024
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How to power GPIO pins on the Alchitry Br
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2
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63
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March 11, 2025
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Lucid V2 test bench help
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3
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58
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March 6, 2025
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Verilog modules are "not used"
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1
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44
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March 6, 2025
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Alchitry AU USB connector
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11
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146
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March 1, 2025
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Alchitry AU (V1) connector STEP file
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5
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49
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March 1, 2025
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Alchitry Cu V2 3D Print Case
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0
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53
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February 28, 2025
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