Hey, new user here. How do I handle inout ports in the DUT in the testbench? Specifically sda/scl for the i2c_controller. I’m trying to simulate the entire Au v1 FPGA, but don’t know how to connect the above mentioned signals to the test bench.
This is a known bug and I opened an issue to track it a little white ago when I wanted to do the same thing Simulate inout · Issue #106 · alchitry/Alchitry-Labs-V2 · GitHub
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