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Trouble monitoring serial transmission on Debian
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3
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60
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April 28, 2025
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Issues with IO Board Template
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4
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119
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April 28, 2025
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no boot for alchitry au
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4
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79
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April 20, 2025
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Alchitry Au mechanical placement of connectors
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7
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142
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April 19, 2025
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Cu + Ft "Unknown port name" and Yosys Failures (V2)
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2
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74
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April 18, 2025
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Moving Projects from Lab1 to Labs2
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14
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128
|
April 17, 2025
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BR V2 board pinout diagram
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0
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57
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April 16, 2025
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Error with counter component in Labs v2
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3
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105
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April 16, 2025
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Supply via USBC
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1
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55
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April 16, 2025
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Alchitry HD Demos?
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2
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81
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April 16, 2025
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How to connect 7 Segment display with Alchitry Au through breadboard?
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3
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99
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April 8, 2025
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Labs 2 Error Message
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4
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65
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March 28, 2025
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Vivado Error Using Labs 2!
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7
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125
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March 21, 2025
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Does bin_to_dec.luc handle negative numbers?
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1
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25
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March 20, 2025
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How to power GPIO pins on the Alchitry Br
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2
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92
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March 11, 2025
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Lucid V2 test bench help
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3
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74
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March 6, 2025
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Alchitry Cu External Clock
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4
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90
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February 27, 2025
|
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Vivado legacy instalation
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1
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45
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February 11, 2025
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AU SPI question (slave mode)
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44
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410
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February 7, 2025
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Do test benches work with Verilog modules?
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4
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84
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February 7, 2025
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Does the serial terminal work with Cu V2?
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7
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116
|
February 5, 2025
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IDE Hangs for large builds
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3
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50
|
January 27, 2025
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Contact to Alchitry shop
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1
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44
|
January 26, 2025
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Yosys error: can't guess frontend for input file
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9
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313
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January 25, 2025
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Unable top create new project
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2
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154
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January 20, 2025
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Help/Question: Need 88 LVDS Pairs for Piano Project
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9
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112
|
January 20, 2025
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Finding a connectors for Alchitry Au Board
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1
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65
|
January 10, 2025
|
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Button problems
|
|
5
|
99
|
December 20, 2024
|
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Au+ Bitstream settings for Quad Mode?
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|
11
|
232
|
December 12, 2024
|
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Verilog top module in V2
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23
|
532
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December 10, 2024
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