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Trouble instantiating Ft module
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3
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109
|
May 10, 2025
|
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Trouble monitoring serial transmission on Debian
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3
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60
|
April 28, 2025
|
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Issues with IO Board Template
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4
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124
|
April 28, 2025
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no boot for alchitry au
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4
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84
|
April 20, 2025
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Alchitry Au mechanical placement of connectors
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7
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150
|
April 19, 2025
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Cu + Ft "Unknown port name" and Yosys Failures (V2)
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2
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79
|
April 18, 2025
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Moving Projects from Lab1 to Labs2
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14
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130
|
April 17, 2025
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BR V2 board pinout diagram
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0
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60
|
April 16, 2025
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Error with counter component in Labs v2
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3
|
110
|
April 16, 2025
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Supply via USBC
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1
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61
|
April 16, 2025
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Alchitry HD Demos?
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2
|
82
|
April 16, 2025
|
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How to connect 7 Segment display with Alchitry Au through breadboard?
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3
|
105
|
April 8, 2025
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Labs 2 Error Message
|
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4
|
66
|
March 28, 2025
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Vivado Error Using Labs 2!
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7
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136
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March 21, 2025
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Does bin_to_dec.luc handle negative numbers?
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1
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25
|
March 20, 2025
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How to power GPIO pins on the Alchitry Br
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2
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97
|
March 11, 2025
|
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Lucid V2 test bench help
|
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3
|
83
|
March 6, 2025
|
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Alchitry Cu External Clock
|
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4
|
94
|
February 27, 2025
|
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Vivado legacy instalation
|
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1
|
53
|
February 11, 2025
|
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AU SPI question (slave mode)
|
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44
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424
|
February 7, 2025
|
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Do test benches work with Verilog modules?
|
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4
|
86
|
February 7, 2025
|
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Does the serial terminal work with Cu V2?
|
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7
|
122
|
February 5, 2025
|
|
IDE Hangs for large builds
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3
|
52
|
January 27, 2025
|
|
Contact to Alchitry shop
|
|
1
|
45
|
January 26, 2025
|
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Yosys error: can't guess frontend for input file
|
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9
|
325
|
January 25, 2025
|
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Unable top create new project
|
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2
|
188
|
January 20, 2025
|
|
Help/Question: Need 88 LVDS Pairs for Piano Project
|
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9
|
114
|
January 20, 2025
|
|
Finding a connectors for Alchitry Au Board
|
|
1
|
66
|
January 10, 2025
|
|
Button problems
|
|
5
|
102
|
December 20, 2024
|
|
Au+ Bitstream settings for Quad Mode?
|
|
11
|
246
|
December 12, 2024
|