I’ve got a custom Element board I’m putting together for the Alchitry Cu V2. It’s intended to handle composite video generation for a CRT TV and interface with an 8-bit computer. On the left side I have an R2R DAC and op-amp, which were easy enough to route. It’s the right side that’s giving me some trouble.
I’m intending to interface this board with the main 8-bit computer motherboard through a standard 40-pin IDC ribbon cable, so I have a 2x20 IDC box header on the right side with various signals that need to be passed between the two boards (data lines, address lines, power, ground, etc). These signals will be coming primarily from Bank A (with 5V, 3.3V, and the “FPGA done” signal coming from the control header).
Does anyone have any tips on how to handle routing between the fine pitch connector and the large through hole connector? I’ve been at it for a few days but am struggling to get a result that doesn’t have a bunch of clearance violations. The positions of the signals on the Bank A connector are flexible, so I can reprogram them for whatever pins make this the easiest. The pinout of the 2x20 header is also fairly flexible; the motherboard hasn’t been finalized so I can still shuffle signals around, though I’d like to keep the ground signals as interleaved as possible.
Post a zoom showing where exactly you have clearance trouble? You’ll have to set your constraints to match the manufacturer’s limits, not something arbitrary and low-tech, of course.
After moving all the FPGA signals to one side of the connector and using vias to get signals over to the far side of the 2x20 pin header, I was able to get everything routed. I was getting some errors saying “solder mask aperture bridges items with different nets” on a handful of the through hole pads and basically all of the Hirose connectors. The ones for the through hole connections went away after I repositioned some traces, and the ones for the Hirose connectors went away after I adjusted each pad of each connector footprint to have a solder mask expansion of 0.05mm (down from the default 0.1016), then saved, closed, and reopened the application. JLCPCB says that’s about how much the expansion should be for SMD pads, so I’m hoping that’s alright.
At any rate, after those changes, this iteration of the routing gets through the design rule checks with no errors, so I’m hoping it’s manufacturable at least. (Bonus if it actually works).
Just some minor critiques, you should place a polygon pour for all the ground pins and vias in the middle of the signal connector. You should also do pours for the power and ground pins on the control connector. This will give you a much lower resistance connection. The way it is routed now will make current favor the pin the power trace connects to. Depending on your current draw, this may or may not really matter but it would be best practice.
Its a little hard to tell from your picture but it looks like you have a four layer board but are routing signals on all four layers. This is causing your ground plane to become broken which will cause signal integrity issues. For a four layer board, you should generally dedicate a full layer to a solid ground plane. This will act as the return path for your signals. Depending on your signal’s speeds this may or may not be a huge deal.
For a four layer board, you generally have signals on the top and bottom and use the internal planes for ground and power. You can sometimes sneak signals onto the power plane if you’re careful and they aren’t critical. If you need more than two planes for signals, you usually want to bump to a 6 or more layer board.
Also remember that most pins on the FPGA are interchangeable. Use this to your advantage when routing. I usually do my best guess when creating the schematic then reorder them all to make routing as easy as possible once the parts on the board are in the correct places. I’d be pretty surprised if you couldn’t route everything between the connectors on just two signal planes using that trick.
Thanks for the tips! I definitely got hung up on the idea that my FPGA pin assignment had to be fixed in place. This is just a two layer board, but I did seriously consider making it a four layer board precisely to help with signal routing, so it’s good to know that that isn’t a particularly good practice.
Thanks also for the note on the copper pours. I hadn’t considered that I might be biasing the current flow to that one pin on the control header. Still have much to learn when it comes to board layout and routing. Lots of little physical things that I’d never even think to consider.
