Br v2, lvds 2.5

[jeff1]

Hello, i’m trying to get lvds to work on the BR V2 breakout board, it seems i can get 3.3 to work, but 2.5 seems to be struggle, i have all the files top, lvds.io verilog, and the constraints, i’m doing a simple loop test, tx-rx p-p n-n, compile works fine, the pins im using are

PINOUT(V2), STANDARD(LVDS_25), SIDE(TOP) {
pin lvds_tx_p B72
pin lvds_tx_n B70 // True differential partner for B72
}

// 2. RECEIVER BLOCK (Contains DIFF_TERM)
PINOUT(V2), STANDARD(LVDS_25), SIDE(TOP), DIFF_TERM(FALSE) {
pin lvds_rx_p B78
pin lvds_rx_n B76 // True differential partner for B78
}

it was advised to use vbsela and vbselb together to get the 2.5 volts, but so far i can’t find vbsela and vbselb on the br v2 breakout board. I have an external 100 ohm resistor between b78 and b76. there are only two files, a top and a lvds.io which is verilog. any help would be appreciated.

regards

Jeff

[Jeff]

these are the two file module alchitry_top (
input clk,
input rst_n,
output led[8],
output lvds_tx_p,
output lvds_tx_n,
input lvds_rx_p,
input lvds_rx_n
) {
.clk(clk) {
.rst(!rst_n) {
dff counter[24];
}
}

lvds_io diff_driver;

// Define a signal to hold the data we want to transmit
sig tx_data; 

always {
    counter.d = counter.q + 1;
    
    // 1. Assign to the signal instead of the port directly
    tx_data = counter.q[23];
    
    // 2. Drive the module with the signal
    diff_driver.tx_single_in = tx_data;
    
    lvds_tx_p = diff_driver.tx_p;
    lvds_tx_n = diff_driver.tx_n;
    
    // 3. Drive RX
    diff_driver.rx_p = lvds_rx_p;
    diff_driver.rx_n = lvds_rx_n;
    
    led = 8b00000000;
    
    // Now you can safely read the signal for the LED
    led[2] = tx_data; 
    led[3] = diff_driver.rx_single_out; 
}

} and the lvds verilog file module lvds_io (
// Single-ended digital connections to/from Lucid V2
input tx_single_in,
output rx_single_out,

// Differential hardware physical output pins 
output tx_p,            
output tx_n,            

// Differential hardware physical input pins 
input  rx_p,            
input  rx_n             

);

// 1. TRANSMITTER: Encapsulate Xilinx Differential Output Buffer
OBUFDS #(
    .IOSTANDARD("DEFAULT") // Inherits bank standard (LVDS_25) from .acf
) obufds_inst (
    .O(tx_p),          // Differential Positive Output
    .OB(tx_n),         // Differential Negative Output
    .I(tx_single_in)   // Single-ended logic input signal
);

// 2. RECEIVER: Encapsulate Xilinx Differential Input Buffer
IBUFDS #(
    .DIFF_TERM("TRUE"),   // Enables internal 100-ohm termination resistor
    .IOSTANDARD("DEFAULT")
) ibufds_inst (
    .O(rx_single_out), // Decoded single-ended output to logic
    .I(rx_p),          // Differential Positive Input
    .IB(rx_n)          // Differential Negative Input
);

endmodule

[gc74]

On the Br v2, VBSELA from Pt maps the the VS pin on the control port, and VBSELB maps to the 2.5 pin.

To get 2.5v, you just need to tie VBSELA high (3.3v) because VBSELB is already pulled high by default. You can also connect VBSELA to VBSELB.