A riscv core on the Cu board

Show and Tell
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I was browsing for an FPGA board to experiment with on a problem I had to solve for work, which I can’t publish. I found this ecosystem and it’s perfect for what I’m doing.

So I’ve built a RISC-V soft core for the Cu, with the Io add-on. If you’re interested (and why wouldn’t you be?), the source is on GitHub and I’ve written a blog series documenting the fun times:

  • The core: RV32E in Lucid V2, multi-cycle, about 81% of the Cu’s logic cells, on a 25 MHz PLL clock.
  • Real C: gcc-built programs run on it, with timer, button and UART interrupts. wfi really stops the cpu clock.
  • vsim: a Verilator front end that draws the Cu and Io, using Alchitry Labs’ own artwork. You click the switches and watch the LEDs.
  • The honest bit: it hasn’t been through riscv-arch-test, so it’s RV32E-ish, not certified.

GitHub: d-o/RISCitry
Blog, starting at part 0: RISC-V soft core 0: Firmware