Hi folks,
I’m tinkering with building a custom DDR memory-controller from scratch on the Au V2. I’m making progress, but as I try to take a more-robust approach, I’ve found some issues.
One issue stems from the fact that the SDRAM DQS lines are not bound to clock-capable pins (SRCC/MRCC). This causes trouble for routing to BUFIO, which is needed to drive ISERDES/CLK. I’ve found that I can route through BUFMRs to BUFR/BUFIO, but there are only 2 per clock-region, and I also need BUFR/BUFIO for the ISERDES/OSERDES output-clock and clockdiv.
I was able to resolve these problems, but it still might be nice to have the DQS on CC pins. It looks like this could be arranged by just swapping the 4 DQS pins (2x p/n) with other nearby pins. For MRCCs, we could swap with D13/C13, E12/E13 (currently mapped to: ddr_reset/ddr_dq4, ddr_a10/ddr_ba0). These replacement pins are right next the the BUFIO/BUFR arrays in the X0Y1 clock-region, where all the other DDR I/O is also placed. For SRCCs, we could swap with C11/C12, E11/D11 (currently ddr_dq3/ddr_dq6, ddr_we/ddr_ras), which are also in the same clock-region as the other DDR I/O pins.
I think the appropriate spec is in fig 3-63 on page 105 of “7 Series FPGAs Packaging and Pinout Product Specification” (UG475) AMD Technical Information Portal I’m comparing that with the Au V2 schematic, and the device-view in Vivado.
I’m pretty new to this stuff, so maybe I’m missing some obvious reason for having the pin assignments the way they are.
Anyhow, ISERDES/OSERDES turn out to have other problems for me, so I’ve made things easier for myself by moving back to IDDR/ODDR, which is much simpler. But it might still be nice to be going through CC pins, for better control of jitter and more-compact routing.