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Does bin_to_dec.luc handle negative numbers?
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1
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25
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March 20, 2025
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Au+ Standard Vivado Project
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2
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481
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June 14, 2024
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How to power GPIO pins on the Alchitry Br
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2
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91
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March 11, 2025
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Lucid V2 test bench help
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3
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74
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March 6, 2025
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Verilog modules are "not used"
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1
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54
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March 6, 2025
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Alchitry AU USB connector
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11
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171
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March 1, 2025
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Alchitry AU (V1) connector STEP file
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5
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65
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March 1, 2025
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Alchitry Cu V2 3D Print Case
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0
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74
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February 28, 2025
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Alchitry Cu External Clock
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4
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89
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February 27, 2025
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V2 on other shops?
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1
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93
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February 24, 2025
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Initial (mixed) success with the new Au v2!
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3
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104
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February 24, 2025
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Vivado legacy instalation
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1
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45
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February 11, 2025
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AU SPI question (slave mode)
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44
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410
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February 7, 2025
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Do test benches work with Verilog modules?
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4
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84
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February 7, 2025
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Does the serial terminal work with Cu V2?
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7
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116
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February 5, 2025
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CLK Generation from FPGA
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6
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164
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February 5, 2025
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Arch Linux - ChacyOS support for Alchitry Labs V2 2.0.24
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2
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188
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January 27, 2025
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IDE Hangs for large builds
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3
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50
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January 27, 2025
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Contact to Alchitry shop
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1
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44
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January 26, 2025
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Yosys error: can't guess frontend for input file
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9
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313
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January 25, 2025
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New Project fails in Ubuntu/kUbuntu with Plasma Desktop
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4
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115
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January 24, 2025
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Vivado MIG generator. Rules OK?
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3
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59
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January 23, 2025
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Unable top create new project
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2
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154
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January 20, 2025
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Help/Question: Need 88 LVDS Pairs for Piano Project
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9
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111
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January 20, 2025
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Alchitry Au board interfacing issue
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3
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177
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January 13, 2025
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Finding a connectors for Alchitry Au Board
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1
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62
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January 10, 2025
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Button problems
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5
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99
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December 20, 2024
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Au+ Bitstream settings for Quad Mode?
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11
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231
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December 12, 2024
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Alchitry Hd - design recomendation
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1
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72
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December 11, 2024
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Verilog top module in V2
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23
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529
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December 10, 2024
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