Hello Alchitry,
I’m wanting to create a player piano driven by solenoids, using an FPGA to send PWM (to control volume) signals over LVDS pairs to my PCBs which control power to the solenoids.
My piano has 88 keys, so I’d need 88 LVDS pairs. Would the Pt board support that? I was trying to understand the product page, it seems there are 54 pairs on top and 12 pairs on bottom?
Thanks in advance, Jon
Hello,
You are right, there is a total of 76 differential pairs.
On top :
On bottom :
If your LVDS frequency is low enough, it may be possible to use the single-ended IO as pairs too?
The FPGA can configure almost any IOs as a pair, but it’s the physical routing on the board that will probably limit the usable frequency.
The base frequency will be 24kHz. As in, 24kHz will be 50% volume because it is 50% duty cycle.
For a shorter volume (and duty cycle), say 1 out of 256, would that be a higher frequency? It’d be like a little (1/256th) blip out of the 24kHz base frequency.
I think you don’t need differential pair at all for 24 kHz.
LVDS is made for much higher frequency (100+ MHz).
From your last post, if you use the duty cycle to set the volume, you don’t have to change the frequency. From my understanding, you need PWM only.
So the project looks like a 88 channels PWM running at 24 kHz, which should work without differential pairs, but this may depends on the wire’s length.
I’m not an expert so I can’t tell if there is a real need for differential signaling at 24 kHz, but so far it looks like it’s not mandatory 
Got it. I was thinking differential pairs would be needed for the cable length that spans the 5-6ft piano.
LVDS is a very specific IO standard and you definitely don’t want/need to use it for this. LVDS requires impedance controlled cables/traces in addition to proper termination and receivers. Way overkill for 24KHz pwm.
In terms of how many pairs their are, actually all the pairs can be used as LVDS inputs or TMDS inputs/outputs. Only some are routed as 100ohm diff pairs but for things not needing perfect signal integrity, the pairs routed as single ended would work just fine. I got 720p60 video out on the Mojo over the 0.1" headers and none of that was “properly” routed (I’m sure signal integrity was marginal though).
Only the dual voltage pins can be used as LVDS outputs though. Again, this doesn’t matter for this project. You can easily send single ended signals in the MHz range many feet with decent wiring.
Just use any pins as single ended signals in reference to ground. Treat ground and your signal wire as a pair over the few feet to maintain good signal integrity. (Keep them close/consistent distance apart) I think you’d have a hard time making it not work because of signal integrity.
What is on your receiving end? A microcontroller? A low pass filter?
Actually just gate drivers then to the power mosfets (and a current sense resistor to check for overcurrent, a fly back diode, a gate and pulldown resistor, but I was mainly concerned with getting the pwm signal from the FPGA to my PCBs).
Is that too simple? How could a low pass filter help?
A low pass filter would effectively turn a PWM signal into an analog one. Your circuit does basically the same thing through the inductor and flyback diode.
I don’t see any obvious issues with what you described assuming the gate driver accepts the 3.3V LVCMOS signal from the FPGA.
Got it. I need to supply 2.5 - 3 amps to each solenoid, and the op-amps capable of that were pretty expensive. I’ll probably stick to the fast-switching route. But I’m definitely open to suggestions on amplifying that filtered analog voltage.