CLK Generation from FPGA

General
1

Hi,
I’m designing a FPGA for custom chip that requires some input CLKs. My question is can I connect those single-ended clocks generated from FPGA to N pins? If No, then can I connect the other digital signals to the N pins?

2

I believe you’re talking about outputting a clock from the FPGA correct? If so, there are no special pin requirements (other than being compatible with the IO standard you need, like 3.3v CMOS).

Care has to be taken when inputting clocks to the FPGA, outputs are pretty free.

_P and _N are only significant for differential signals or clock input buffers (as the buffer only connects to the _P pin).

3

Thanks. This answers my question about output clocking.
As for the inputting data, I would have high-speed data coming from the chip to FPGA. Is there any constraints on those data other than complying with 3.3V CMOS? Can those be connected to P or N? Would I have crosstalk if I use P or N pins for two channels?

4

Define “high-speed.”

If you’re running at LVCMOS33 (the default IO standard) then you can get a few hundred MHz out of the IO drivers. You should have no signal integrity issues at these speeds (or any speeds the FPGA is capable of) with any IO caused by our board. For faster than that, you’ll have to switch IO standards.

Maybe take a look at the Ft+ schematic. All of these signals run on a 100MHz bus and are packed densely on the headers.

The pinout and connectors on the V2 boards are marginally better than the old ones but I never saw any major issues with the old ones.

Will you have crosstalk between two pins next to each other? Yes. Will this be enough to matter? Almost certainly not (again depends on exactly what “high-speed” means).

5

Thanks.
By high speed, I meant in the order of 100MHz.
I got my answer.
Appreciate your help.

6

100MHz is pretty high speed, but the edge rate is a much more important figure to determine if you need to apply high speed SI trace and route geometry

7

This is true, but the edge rate is strongly correlated with the required frequency. With the Au, you can set slew and drive strength to manipulate the edge rate.