This is not a critical error, but annoying. When I have verilog modules that are instantiated inside of a verilog_top module that is then instantiated in lucid_top, the sub modules are said to be not used, even though they clearly are and are even outputting signals to LEDs.
Yeah this falls into the “Verilog support lacking” bucket of bugs. Proper support is planned but is a major feature/tons of work.