Button problems

Help Request
1

So I have been doing a project in which I need the button on the old Au to trigger a process. I am using the rst signal because I assumed that it was debounced, and I checked the tutorials just to be sure, and it seemed to be debounced. Is the rst signal actually debounced?

Edit: when I use:

always @(posedge clk)
begin
    if(buttonp == 1'b0 && button == 1'b1) // if button is pressed, do something
    begin
        count <= 1'b1;
        counter <= 8'b0;
    end

when the FPGA boots up though, without me pressing the button, the if statement thinks that the button was pressed and the cycle begins, or it would if it worked now.

when using a standard posedge block, this does not happen

2

The reset button is active low, so the signal is high when the button is not pressed.

But the FPGA possibly initialize with the signal low, so it immediatly transition from low to high on start?
Maybe it’s the issue?

3

I am using the rst signal, not the button input. The rst signal appears to be active high, I tied it to led[7] and it lights up when I pressed it. That is what is confusing me. The main question I have is if that rst signal is debounced, and why on earth when the FPGA boots up, the verilog detects a button, only when I use this method to detect posedges:

always @(posedge clk)
begin
if(buttonp == 1’b0 && button == 1’b1) // if button is pressed, do something
begin
count <= 1’b1;
counter <= 8’b0;
end

and not a regular always block.

4

I’m not sure but maybe the button signal is not initialized to 0, maybe you need to add an initial block to set it to 0 on start?

5

That could cause the problem, but button is an input, and its just rst, so if rst starts low, then theres my problem. The other signal, buttonp is initialized as button, so that would make sense.

6

The reset_conditioner (the source of rst) does not debounce the button input. Take a look inside the module. It uses a chain of DFFs with their input set to 0 but they reset/are initialized to 1. This creates a pulse of at least STAGES clock cycles long synchronized to the clock.

It will output 1 when the FPGA starts for a few cycles.

Check out this tutorial. It is an older tutorial but the contents are still good.

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