I was trying to write a memory module in Verilog, following the patterns given by the components provided in Labs. It wasn’t working so I wrote a test bench and started whittling away. I now have “ram” that just writes a constant value all of the time while my test bench shows it as a undefined.
Code follows.
The module holding the place of RAM.
module verilog_ram (
input clk, // clock
output reg [8-1:0] read_data
);
always @(posedge clk) begin
read_data <= 8'h20; //ram[address];
end
endmodule
The test bench.
testbench test_verilog_ram {
sig clk
fun tick_clock() {
clk = 1
$silent_tick() // tick without capturing signals
clk = 0
$tick()
}
.clk(clk) {
verilog_ram ram
}
test myTest {
clk = 0 // initialize the value
$tick() // capture initial state
// test goes here
repeat(8) {
$print(ram.read_data)
$tick_clock()
}
}
}
The result.
Running test_verilog_ram.myTest...
ram.read_data = {xxxxxxxx}
ram.read_data = {xxxxxxxx}
ram.read_data = {xxxxxxxx}
ram.read_data = {xxxxxxxx}
ram.read_data = {xxxxxxxx}
ram.read_data = {xxxxxxxx}
ram.read_data = {xxxxxxxx}
ram.read_data = {xxxxxxxx}
Done.
When I had my real attempt in the RAM module, I was getting undefined coming out. I assumed originally that I had an issue with my write to memory. This points to an issue with the read, or with the way the test bench is interacting with the Verilog module. Any thoughts?