It looks like the FPGA’s CCLK starts at 3 MHz read the bitstream header, and then switch to the value provided by the ConfigRate field defined when the bitstream was generated, which defaults to 3 MHz but can go up to 66 MHz.
So we don’t need a big beast, and after better looking, I have one of these cheap 24 MHz usb ones (I thougt it was much slower) that may be enough, but I still have to hook it on the flash ship without damaging my Au, since the SPI bus is dedicated for this and thus not exposed on the connectors.
I may try it when I find some time 