The Pt is the first Alchitry board which has different top and bottom pinouts. Had you made that assumption with any other board, you would have been correct! The previous boards work in the fashion you were expecting. The reason this was done on the Pt is that it uses a larger chip footprint with vastly more GPIO. There’s (approximately) twice as many pins available. I expect that splitting the top and bottom connectors into being separate sets of GPIO was the most feasible option for getting more GPIOs off of the board. Figuring out the alternate constraints to route to the top or bottom connector is a hurdle, but a relatively small one.
Hah, I screwed up the USB3 cable thing too! I got everything working, and was like, “Why is the bandwidth so low? Why is the low bandwidth suspiciously close to the max USB2 bandwidth?” (narrows eyes)
The knowledge that the top and bottom connectors are different on the Pt was covered extensively in the forum thread where the new v2 boards were announced and discussed. Which is more or less that “background reading” you theorized. I have to agree that it could be better documented 