+1 for the Zynq ^^
Will the PCIe adapter also have a classic or M.2 port for use with a PC?
I believe the initial v2 board shipments are very close? I’m excited! I’m not 100% sure I will be able to use the v1->v2 board converter to use it immediately in my project (you note some incompatibilities, and I haven’t dug through the details to see if they affect me or not), but if I have to do a board spin on my end, that’s no big deal. I will just be a little happier if I can play with the new board right away. Updating to something that can just directly use the new Hirose connectors instead of my janky Br-based solution is on the roadmap anyway.
A standard PCIe adapter would be a separate board. I’m not sure there’s much demand/use for one?
All the V2 orders without a Pt should ship today! I programed and tested the first batch of Au yesterday and I’ll pack them this morning.
The incompatibilities with the adapter are basically all from Bank D. Some pins don’t exist anymore (uart lines) and the dual voltage pins act differently. Also the clock inputs don’t line up for the Cu (had to choose between the two). Other than that, you can just slap a V1 wrapper around the old pin names and it works.
Thanks for confirming! That’s what I suspected, reading your comments on the schematic. I don’t use bank D for anything so I should be good to go.
Separate question: when i get the Au v2 and it supports the full 800MHz sdram speed due to the higher speed grade, is the ui_clk coming out of the MIG interface related to the input clk? Or will i still need to do clock domain crossing because they are unrelated 100MHz clocks (like we do for the FT600 because that clock definitely is unrelated)
Just my tuppence worth.
I love my alchitry AU boards (I have 4 of the 35T and 1 of the 100T).
I’m working on a product that will use these, so I guess my big question is, what happens to the old ones? I assume they won’t be available and I’d have to change the design of my board?
I like that the connectors will be a more common part (I can only find the current connectors via sparkfun, which is expensive).
With regards heat, I agree being able to at least get a heatsink on the chip would be a huge help, could I make a suggestion? Put headers on both sides? as you did with the BR? That would give people the option and also mean you could still see the LEDs for debugging when the AY is mounted on your own board (currently impossible without a cutout and running your own board upside down).
Might II also suggest an “AU Light” ? something without the DDR RAM and perhaps an extra connector for those of us who crave all the IO we can get, but don’t use the DDR?
Do you have an ETA for launch? I need to consider if I should look at new connectors or not.
I was thinking about a standard PCIe carrier board so that we can connect the FPGA to a PC for accelerator/coprocessor usages, where a software on the PC could offload specific processings to the FPGA.
I don’t have any plan right now but it looks like Xilinx already offer some of these through Vitis for AI related tasks.
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The V2 boards are available right now!(Excluding the Pt)
Adding connectors to both sides would raise the cost of the board around $10. This would be paid by everyone and most people don’t have heat issues.
There is a case to be made for putting connectors just on the bottom, but this felt wrong for a lot of boards like the Io where you’d have “tops” on both sides.
I’ve also found the bottom connectors to be the more delicate of the two. If you disconnect them wrong (try to open the boards like a hotdog bun instead of lifting near the USB port) the short ones can break. This usually happens on the less expensive board now. I’m planning on making a video to demonstrate the best way to connect/disconnect them. When used correctly, they’re very solid and I have a set of Br I’ve been using basically as fidget toys to test them with likely thousands of cycles.
The Pt does have connectors on both sides. There was some debate around breaking out a maximum number of IO on one side vs being able to use boards on both. Ultimately, it seemed more useful for more cases to be able to design around the base form factor and be able to add stuff independent on the other side. Like adding an Ft+ on the bottom for a lot of bandwidth without taking any front IO.
I’m still toying with the idea of an outrigger style board that brings the top connectors around to the bottom for heavy IO applications.
As for a PCIe card board, I don’t there are any practical reasons for this other than toy examples for a modern PC. The FPGAs just aren’t that powerful compared to a GPU. Using them with something like a raspberry pi makes a lot of sense for fast IO or compute as the Pi is more limited. If you can convince me of a good use case for pairing with a desktop, I’d love to hear it.
Ahhh, I missed that news, thank you!!
I’ll go take a look 
I don’t have actual plans yet but I could list a few ideas so far :
- Learning PCIe and drivers
- A fast and customizable logic analyzer
- High bandwidth communication with external interface
- Compatibility bridge for no-longer supported hardware
- Custom capture / process / display / live incrustation, etc. using the Hd
- Custom helper co-processor / hardware emulator
Most of these idea are beyond my skills though XD
For learning about PCIe, the raspberry pi I think will provide a much better platform. Loading PCIe drivers requires a reboot so doing it on the system your developing on is a nightmare. Not to mention any driver crashes can take out the entire system.
Stuff where you need to interface with the external world is hard from inside a PC case. Most of those use cases are probably better off with the Ft+ (although the GTP offer significantly more bandwidth).
I don’t think the board would be too complicated, but it’s just low on the list for now.
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I’ve been looking at the various boards, great to see the use of known connectors for high speed stuff.
I also REALLY like the new BR layout (so many times I’ve gotten confused were the raw, gnd and 3.3V pins are).
Are there plans to make a BR board (in the wide version perhaps) to sit under the Pt version? So that you can use the upper BR and a lower BR?
I think the Br with connector on both side can go on both sides of the Pt?
That’s correct, the Br could be used on either side of the Pt, same with any board not using the tri-voltage pins (as that’s where the GTP are).
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Fabulous, thank you for the clarification
If there is a possibility of making a PCIe board for PI5, couple of suggestions:
-
standard pcie connector. Wwaveshare makes a several different pcie expansion boards using pcie switch chip, see here https://www.waveshare.com/product/raspberry-pi/boards-kits/raspberry-pi-5/pcie-to-pcie-x1-board-c.htm standard breakout
use a standard pcie connector. -
16PIN PCIe connector (PCIe Gen2/3 x1) here is a compact Nano Base Board (B) for Raspberry Pi Compute Module 5, Same Size As The CM5 | CM5-NANO-B board with the connector.
The board would also have break out for I/O’s for prototyping.
The plan was to use the same 16 pin ribbon that’s used by the Pi. I believe it’s the same as the Nano Base Board you linked.
If enough people want one, we could make a standard PCIe board. Although, the first board you linked could be used with the 16pin ribbon cable version.
I would absolutely buy something like that.
I’m a software dev, without any use case for FPGA and I ordered everything that alchitry offers for learning purposes.
With a PCIe carrier board I can start to see some actual benefit for me where I’d be able to integrate the FPGA with my software solutions.
I still don’t have a concrete idea but it would be excellent and fun learning opportunity.
The point is, I’d probably buy 2 of those so I could have 2 cards doing different stuff and if trough testing and tinkering I find a real benefit then who knows how many I’d need if I started shipping an app that relied on an fpga.
To me this seems like a great idea.