I’m currently working on potentially creating a new Alchitry board based on the XC7A100T-1FGG484C. This would bring a big boost in IO, LVDS 1.8V support, and GTP 6.25Gbps transceivers.
I’m curious what anyone interested in this would like to see as part of this board.
With the potential for a Pt+ with a XC7A200T, cooling would become a major issue. I’m considering changing the connectors/footprint of the board and wanted to know how important backwards compatibility is with the current boards.
These are all just loose plans right now and I’m trying to gauge the demand for this.
the speed rating for the XC7A100T-1FGG484C is -1, I think for Fiber Channel (FC) the rating is -2, or Vivado does not recognize it for GTP transceiver work. I’m currently using a XC7A100T-2FGG484I, (speed rating 2) but I would prefer alchitry boards and environment, the development system is very nice.
This is good to know. Looks like a handful of the high end networking cores require -2. I’ll look into the cost difference but I’m pretty sure -2 will be the way to go as the GTP transceivers are the major upgrade over the Au.
Hello, it feels very nice to be asked for participating in the new design!
Here are my thougt so far :
Changing the footprint whould make it incompatible with the Au/Cu shields, which would be pretty sad, it would be confusing as we would need new Pt specific Io, Ft and Br.
If it would be possible to keep this compatibility by adding new Pt connectors in a dedicated area instead then replacing, I think it would be the best way to go.
Maybe by making the bord longer to the right so that all the Pt additional IOs are there and we can use Au/Cu shields on the left side and Pt shield on the right?
Or having the new connectors on the back of the board like front gets Au/Vu shields and back gets Pt?
If cooling becomes an issue then it may be needed to have the FPGA aside of the shields (making the board even bigger) or all connectors on one side but the FPGA on the other side, allowing to mount a heatsink?
All the boards are getting redesigned with a new smaller footprint (55mm x 45mm) and new Hirose connectors.
Without getting too deep into the weeds, these new connectors solve a lot of problems with the old ones. They are widely available for people to make their own boards, they have better signal integrity (especially the 1.5mm version), and I’ve been able to source them for a bit less than the old connectors (especially true of the plug side). I think I’ll be able to make a Br without top connectors available for $5.
The Au/Cu will have three connectors on the top. One 50 pin for power/control and two 80 pin for GPIO. There will be an adapter available that will convert from the new to the old layout so you can use your existing elements/custom boards.
About half the signals are routed as 50 ohm single ended and the other half are routed as 100 ohm differential pairs (current board doesn’t have controlled impedance). The dual voltage pins are now 2.5V instead of 1.8V to allow for LVDS_25 outputs (this was an unfortunate oversight on my part with the original). The Au will now have the -2 speed grade FPGA. The Au’s power supply has been revamped to allow 5-12V input and outputs up to 4A on the 3.3V and 1V rails.
The Pt will have the same connector setup except on the top and bottom. The bottom connectors will have the GTP transceiver signals and allow for the short 1.5mm 20gbps rated connectors. You’ll be able to stack boards on both sides of the Pt and have them operate independently.
For cooling, I’m working on a board you’d stack that will make space for a heatsink and potentially a small fan.
I’ve had some Br V2 boards made mostly to see how I like these connectors. I’ve been using two of them as fidget toys, plugging and unplugging them. The new connectors have held up well and have a nice click to them when they engage.
If you’ve tried to buy a board in the last year or so you may have had issues with them being out of stock at SparkFun. With this redesign, I’ll also be taking back manufacturing. SparkFun will continue to sell everything but we will also have our own store again. SparkFun has been going through some growing pains on their manufacturing line so by taking things back I’ll be able to keep things in stock and get new boards made.
There’s a lot working its way through the pipeline.
Basically the same except there are also now two 1.35V pins broken out (so technically 104 pins). These are on the DDR3 bank but aren’t used/disconnected on the current Au.
Where possible, the single ended pins were used for the LEDs freeing up another differential pair as well. The only singled ended pins are now a pair of dual voltage pins and the pins connected to the QWIIC connector.
Hello,
I appreciate the effort of creating the new Alchitry Platinum board. Although I have developed few boards based on early Xilinx chips about 30 years ago, I have switched to Altera chips later on. Seeing this effort here, however, makes me want to come back to Xilinx (the Intel free tools seem quite stale now).
What I like the most is the modular design approach on Alchitry. In my application I am doing a lot of high speed (20 - 100 MHz) data acquisition, and equally fast control. For that, good, fast connectors with plenty of LVDS (mostly 1.8V) signals is the most critical requirement. Therefore new connectors choice is a very significant improvement. Also, Having the fast USB3-based communication implemented directly on the main board would be most preferential (one extra USB3 connector plus one FT600 chip, even at the cost of making the board slightly longer, but freeing ~ 20 pins on the connectors for IO signals), or possibly doing both communication and programming using the FT600, if that is possible.
I realize that this wish may not reflect the community preferences and may not be considered. Still, I am excited to see this effort, and I am purchasing now the older 35T + FT600 board to refresh myself on Vivado.
Hi,
It is good that you take into account that the module can be powered by a higher voltage. The current modules use the ADP5052 chip, which can handle up to 15V. I have tested the operation of the current module on 12V for a long time. I recommend to keep the current max 15V for planned new modules and also to add some overvoltage protection like TVS on the input. e.g. PESD12VL1BSLAZ.
Another useful thing for new version would be to lead the USB3 connector pins (D+ and D-) to the internal connectors. This can be useful if you want to use this USB connector in projects and bring your own connector elsewhere on the board,
With the Pt, you’ll be able to throw an Ft on the bottom and keep the top 104 IO free while getting USB 3. Adding a FT600 to the main board would take away a lot of IO. Every IO pin is broken out so it’s not like we could just magically get 20 more if the Ft was built in. The FT600 also couldn’t program the FPGA (you need a JTAG interface).
I also have plans for an Ft+ with an FT601 (double IO pin requirement but double the bandwidth).
All of the differential pairs are capable of LVDS inputs (technically 2.5V but often compatible with 1.8V) only the dual voltage pins are capable of LVDS 2.5V outputs. This is a limitation of most the Artix chips not having HP IO banks. I think there is only one package that has any HP banks.
Powering the current boards with 12V is a little spicy. The decoupling caps on the Au are rated for 16V so they’re likely fine when new but over time may fail at 12V. The values for the switching supply were also tuned around 5V.
EDIT: I was just looking at the datasheet for the ADP5052ACPZ and powering the Au with anything over 6.5V violates it’s ratings. The EN2 pin is tied directly to VCC and the absolute max rating for this is 6.5V.
The new board will survive 15V (ADP5052ACPZ is still used) but it’s tuned for 5-12V. Caps are upgraded to at least 25V.
The USB power input also now goes through an “ideal diode” (LM73100) instead of an actual diode and is protected by a 5V TVS diode.The main “raw” input doesn’t have a TVS diode on it but if you’re hitting the connectors with ESD, you’re gonna have a bad time.
You can’t simply also route the USB signals to the FT2232 and the external connectors. You would likely end up with signal integrity issues when stacking boards (long stubs).
The ft on the bottom should work quite nicely, I haven’t realize that this is the option (I only got to your site yesterday, got excited about, and this was actually the first time ever I have posted anything).
I like the idea of using the 601 chip, a good chance of running the full USB3 bandwidth. Please do so.
I was working on the pinout of the Pt yesterday and had some extra pins that couldn’t be crammed onto the headers. I used them to enable the FIFO interface of the FTDI giving it 40MB/s instead of a max of about 1.2MB/s over serial. Not quite the 200/400MB/s of the FT600/FT601 but a nice boost to the built in.
I just found out that because the synchronous FIFO mode can only be on channel A and JTAG is then on channel B, this breaks compatibility with using Vivado directly. The program_ftdi utility assumes channel A is the JTAG channel.
I could switch the FIFO interface to channel B and use the async FIFO interface instead but this limits data rates to around 20MB/s.
So the choice is maintain compatibility with Vivado’s hardware manager or get double the bandwidth. I’m leaning toward double the bandwidth and just require the Alchitry Loader.
I like the Vivado compatibility because it allows the usage of the soft ILA module, which is quite usefull for debugging.
It also makes the board easier to work with when working with Vivado by using the built-in programming feature.
I wonder what happens if we use the program_ftdi program and then use the FTDI tool to swap the channels? Would the FTDI driver automatically maps the JTAG calls to the suitable channel?
My experience with the FTDI stuff if you have to select the channel from your application. I assume Vivado always chooses channel A. Their docs seems pretty explicit about it.
I just changed the schematic to use async fifo on channel B. This actually frees up two IO pins making me able to add a global clock input to bank A and replace all the LED IO with independant IO on the control header. I like this.
EDIT: Forgot to address the second question. I don’t have any plans for Ultrascale but it’s not out of the question eventually. They are a bit out of the price range I’m looking to hit now.
Oh so the LEDs have thier own dedicated pins? and we have a dedicated clock pin? Nice!
I was wondering of possible conflicts caused by the LEDs when we use the exposed shared pins for something else on the Au.
Is the new clock pin an input pin so we can feed a custom clock to the FPGA or will it be bound to the board oscillator (100 MHz)?
EDIT : Sorry I read too fast, this question is already answered XD
About the US, yes I thougt about they are quite more expansive than the gen7, the Au is already pretty pricy for most tinkerers XD
There are actually a handful of clock inputs on the current Au and spread across the headers on the new boards. The major difference is this time around I’m standardizing their location’s as much as is practical.
The IO pins used for the onboard LEDs on the Au are also broken out on the “control” header (similar to bank D on the current board). With the Pt, I had enough extra IO to give those 16 spaces (8 top, 8 bottom) their own IO pins. The QUIIC connector and LEDs don’t share any main connector pins on the Pt but do on the Au.
Oh so all the V2 and maybe future boards will have the clocks pins at the same places?
Would make extensions more future-proof, which is good!
The IO pins used for the onboard LEDs on the Au are also broken out on the “control” header (similar to bank D on the current board). With the Pt, I had enough extra IO to give those 16 spaces (8 top, 8 bottom) their own IO pins. The QUIIC connector and LEDs don’t share any main connector pins on the Pt but do on the Au.
Oh yes that’s what I meant, the LEDs having dedicated pins frees up the ones ont the connector, but only it’s only on the Pt, and ofc we can still bind them back together in the fabric if we need, FPGA rocks XD
So if I understand everything correctly :
Vivado compatibility is kept
It’s probably possible to use the FTDI tool to change channel B to serial if needed for backward compatibility to V1
Au V2 gets 2 extra pins compared to V1
Pt have all the connectors on both sides (1x control + 2x IO on each side)?
And all IO pins are independants? (So the Pt have almost twice the IO of the Au? )
There will be cheap adapter to use V1 extensions on V2
Maybe cheap adapter to use V2 extensions on V1
A spacer make room for a heatsink
Sound pretty nice so far! I hope the Pt will be in my budget XD
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