The Pt actually has more than twice as many IO if you include the 16 extra on the control headers and the GTP (6.25gbps transceivers) on bank D (underside of bank B).
There will be an adapter to use V1 boards with a V2 FPGA but I wasn’t sure if there would be demand for/the difficulty supporting V1 to V2. If enough people want a V1 to V2 board I could try and get some of the connectors for it. Getting clocks to line up can be am issue though.
I’m planning to get the first batch of Au made pretty soon. I’m just waiting on some of the parts to arrive. Once I can confirm it’s good to go, I’ll open up orders. They’ll be available by the end of the year. I’m hoping to maybe even take some discounted preorders on Black Friday.
The Pt will be a bit longer. Likely February or March.
What about Ft boards with the new connector footprint? I definitely need an FT600 in my project, so it would be a choice of figuring out how to successfully route one on my own board, or add a new-connector Ft to the stack.
I suspect figuring out how to route a FT600 on my own probably isn’t that bad, but it’s still a fair step up on challenge rating from what I’ve done so far. I’ve only been doing my own PCBs for a year or so. I would certainly start by looking at the Ft design.
I’m aware of the adapter, and that doesn’t quite work either, because the thing still needs to plug into my board, and the whole point of the v2 is to avoid the v1 connectors. It becomes a nice compact improved solution only if the whole stack is the new connectors.
In the meantime, what I have works well enough- I have an Au, an Ft, and a Br with female headers soldered in, which then plug into blocks of male headers on my project board. It works well enough as a prototype, but for a hopeful finished product, it would be a huge improvement to have a v2 of the Au and Ft.
The Ft+ is exciting, but really only applicable if I went all the way to the Pt, because it sucks up a lot more pins. But with the Pt, I could put the Ft on one side of the Pt, and my own board on the other side, and have the full complement of pins for my board plus getting the 24 pins back that the existing Ft takes up from the IO space. There’d also still be a lot of pins available on the far side which the Ft/Ft+ isn’t using, but those would be annoying to get at from the main PCB.
I’m sure the Pt is going to be quite expensive, presumably in the ballpark of the Au+. And that’s not something that can be gotten around, the bulk of it is just the price tag on the bigger FPGA model.
Yes, it’s the same FPGA than the Au+ but in a different package with more pins exposed, and with faster speed-grade, so definitely pricey, I just hope I can afford it
If you plan to use a v2 with you existing project, beware that the Br v2 pinout is different!
As you can see on the picture from Justin, all the power supply pins have mover to the Control port. All baks pins are IO except for 4 ground pins on the left, so if the V+ and/or R pins are used by your board, it won’t work with the Br V2 because V+ and R on the Br v1 are now grouns and/or IO.
At least it should not be dangerous, But if your board in powering the FPGA through the V+ or R pins, then it will cause a short.
If you are in this case then you may have no other choices than to stay on v1 Br + adapter or design a new board for v2 (in this case you may use the new connectors directly so you don’t even need to sandwich the Br in-beetween).
In my case I plan on getting a Pt + adapter (maybe even 2x if they are cheap for use on both sides if needed) + v2 Br so that I can reuse my v1 Br, Ft and Io and access the Control port.
I may get a Cu v2 one day if it exist to try out smaller Lattice FPGAs too.
Oh, I wouldn’t be using a Br v2 at all. The big thing drawing me about the v2 project is better connectors that will be easier to get the factory to source and place, and I would just have the right connections specified for everything on the PCB (which would, yes, require specific new routing). I’m still very new at PCB design, only been doing it for about a year, but I did study all this stuff in college (decades ago), and it’s coming back fast. And so much of it is so easy now! We live in the future!
The Ft, Ft+, Io, and Hd will all likely be available by the end of the year as well.
The Cu will be a little after that.
The Br V2 and original Br won’t physically line up in addition to having different pinouts. I’m also planning a new Br variant that breaks the pins out on the sides since the 4mm stack height (current boards are 6mm) can make it tricky to deal with anything hanging below the board.
You will likely be pleasantly surprised by the price of the Pt if things go according to plan.
Oh so we even get HDMI?
I saw that there are 2 kinds of HDMI modules : passives ones that directly connect the plug to the FPGA, and active ones that use a chip that handles all the HMDI protocol and clocking and connect to the FPGA with a FIFO-like or parallel port interface.
Which kind the Hd will be?
A “wide” Br is a good idea, I may get me one for uses cases when I need the Br + the Io in the stack
Hi Justin,
Please consider changing the placement of the FPGA chip to the opposite side of the board from the connectors for better cooling. If the board is mounted in another board, it is not well cooled and also some kind of passive or active cooling would be misplaced. see picture, please.
Jan
I admit I thought about this but I realized that the board looks upside down when used with the Io.
I guess the spacer is supposed to solve this by allowing to mount an heat sink in between, but it would be the best to have it on the open side when the board is plugged.
This is not an issue on the Pt since it will have connectors on both sides, but will be on Cu/Au.
Maybe these would need connectors on both sides too, but with the pins shared?
Additionally to the FPGA being exposed for heat sink mount, this could allow nice uses case where we could have the board plugged on a custom board + an Io on it for debugging.
Having connectors on both sides on the Au+ sounds like a great way to provide some flexibility, although with some additional manufacturing cost. It should be kept in mind though, that the connectors are still male/female, so the Io board trick would only be possible if the gender of the connectors onto the main host board was chosen to let the Io board face outward.
Yes, you’re right, I assume that the bottom connectors on the FPGAs are male, so that the extension boards are not flipped when we stack them on the bottom.
So indeed the recommended choice for host board would be to have female connectors to have the FPGA face outward.
Ofc the cost of these additional connectors on Au/Cu and the additional routing must be considered, since it looks like Au v2 seems to be already pretty far in the design, maybe it’s too late for such a big change.
The Hd will be directly connected to the Au. I actually have had an Hd ready for the current boards for a while but, long story short, SparkFun didn’t know when they would be able to start making them which kicked off everything.
The Au will keep the connectors on the top. Admittedly, when used as pictured my @LMN128 cooling could be improved. However, cooling if rarely an issue on the Au.
The PCB acts as a pretty decent heatsink and the new one will be even better. It is going from 6 layers to 8 with triple the solid ground planes that will conduct heat well.
I’ve played around with slapping heatsinks to the Au/+ and it doesn’t seem to make a substantial difference without active airflow and even then the PCB generally does a great job.
The Pt and Pt+ could be a different issue with some real heat generation potential. I’m kicking around solutions for an outrigger like board that would allow all 6 connectors to connect to a PCB on the bottom for use as a module.
Ok so it’s a passive one, so I have a question about the Pt : would using the GTP allows for higher resolutions?
If it’s so, it would be nice that the Hd connects to the GTP pins on the Pt, so that it can take advantage of faster speed when stacked on the bottom of Pt, while still maintaining compatibility at lower speed on Cu/Au and front side of Pt?
The Artix -2 speed grades support all HDMI 1.4 resolutions (ie 1080p60). The GTP can’t be used for higher resolutions directly.
HDMI requires TMDS_33 as the IO standard and the GTP are LVDS (much lower voltage).
Heat inside an enclosure depends on a ton of different factors so it’s impossible to say. The amount of power an FPGA consumes (and in turn heat produced) is highly dependant on the design loaded onto it.
If your design is consuming enough power and is in a box with poor air flow, then adding a heatsink isn’t going to make a significant difference. A small fan blowing air through your enclosure would.
So it would be possible to use the GTP for higher res (or more fps) but it would need level shifting?
DisplayPort looks like 3.3v too so I guess same thing?
About the heat, does the FPGA itself have any safeguard like automatic shutdown in case of overheat?
If not, is it possible to implement it in our design using the built-in XADC and/or monitor?
I think about a simple module that would monitor the temperature and stop the clock and/or raise an error signal to selected parts of the design in case of overheat?
It might be possible but it’s not as easy as traditional (slow speed) level shifting. You’d likely be better off using the GTP to interface with an HDMI controller/PHY.
According to the docs, the GTP can do a swing of 1V. Far less than 6.6V you’d see on TMDS_33.
You can use the internal temperature sensor and XADC to get the internal temp and slow/stop parts of your design. This isn’t automatic. I’ll likely do a tutorial on this at some point.
