Yosys Pipeline Error with 2.0.37

Help Request
1

I’m instantiating a pipeline like this:

    .clk(clk) {
        edge_detector trace_clock_falling(#RISE(0), #FALL(1))
        #DEPTH(2) {
            pipeline trace_oe
            pipeline trace_data[8]
        }
    }

which ends up giving me

Starting yosys...

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.52+117 (git sha1 bfe05965f, clang++ 18.1.8 -fPIC -O3)

-- Parsing `.../Projects/alchitry/ft-tmpl/build/source/pipeline.v:22: ERROR: Can't resolve function name `\type'.
mpl/build/source/alchitry_top.v' using frontend ` -vlog2k' --

Line 22 in the offending autogenerated file is:

function automatic [((($bits(type($bits(D_pipe_q))) > 1 ? $bits(type($bits(D_pipe_q))) : 1) + 0) >= 0 ? ($bits(type($bits(D_pipe_q))) > 1 ? $bits(type($bits(D_pipe_q))) : 1) + 1 : 1 - (($bits(type($bits(D_pipe_q))) > 1 ? $bits(type($bits(D_pipe_q))) : 1) + 0)) - 1:0] sv2v_cast_0F88E;

Is this something that I’m doing wrong?

Thank you!

2

It’s most likely a bug. Can you share the full project so I can easily reproduce and fix it?

EDIT: Scratch that, I was able to reproduce it.

3

I fixed the issue for most cases. It’s likely still possible to break it if you try but should be very unlikely now.

It seems to happen from nested $bits() functions and SV2V (system verilog to verilog converter needed for Yosys) adds a weird type() wrapper.

In most cases now, the width of a value will be used instead of $bits(value) like it does now. That means this should not happen very often.

TL;DR; it should be fixed in the next update that will be pushed later this week.

1 Like
4

Thank you - Much appreciated!