Does anyone here know how to configure an output on the Au to be pulldown?
I am doing stuff with the leds, and it appears that they are not pulled down when not forced to be logic one.
You have to set it in the XDC constraint file :
set_property PULLTYPE PULLDOWN [get_ports {led[0]}]
Also, depending on your code, the synthesis tool may automatically generate latches so your pins may keep their last state when they are not actively driven.
If you really want to set an output pin to high impedence (aka pullable), you have to set it to z instead of 0 or 1.
Thank you, for some reason I did not think of that 
Note: “PULLDOWN” is not supposed to be capitalized:
set_property PULLTYPE pulldown [get_ports {led[0]}], and even then I have some problems that I am working out.
Sorry, I am a newbie.
OK, for more newbies like me, you have to declare the pin: pin led[0] LED0
and then describe it: set_property PULLTYPE pulldown [get_ports {led[0]}] LED0
as a pulldown or pullup. Sorry if my example might not be the best.
Sorry I assumed you used the premade XDC offered by Alchitry
You don’t have to declare the pins as long as you use names of existing ports of your top module.
My example assumed that your module have a multibit output port named “led” like this :
For each bit of this 8-bit port (because there are 8 leds) you need to have at least these 2 lines in you XDC :
set_property PACKAGE_PIN K13 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
The fist line tell which physical FPGA pin (here K13) to bind to led[0], which is the first bit of port named “led”.
The second line sets the voltages used (here 3.3v, from the LVCMOS33 keyword).
Then to enable the pulldown, you can add :
set_property PULLTYPE PULLDOWN [get_ports {led[0]}]
the same goes for “led[1]”, “led[2]”, etc.
Note that you can use several XDC in a project, so you can use the Alchitry one as is, and then add a second one with your customizations, you don’t have to copy paste anything, the 2 files will act as a single one in the end.
Huh. My .acf file looks like this:
clock clk CLOCK 100MHz
pin usb_rx USB_RX
pin usb_tx USB_TX
pin rst_n RESET
pin led[0] LED0
pin led[1] LED1
pin led[2] LED2
pin led[3] LED3
pin led[4] LED4
pin led[5] LED5
pin led[6] LED6
pin led[7] LED7
set_property PULLTYPE pulldown [get_ports {led[0]}] LED0
set_property PULLTYPE pulldown [get_ports {led[1]}] LED1
set_property PULLTYPE pulldown [get_ports {led[2]}] LED2
set_property PULLTYPE pulldown [get_ports {led[3]}] LED3
set_property PULLTYPE pulldown [get_ports {led[4]}] LED4
set_property PULLTYPE pulldown [get_ports {led[5]}] LED5
set_property PULLTYPE pulldown [get_ports {led[6]}] LED6
set_property PULLTYPE pulldown [get_ports {led[7]}] LED7
I was going to ask, where do i find information on what pins are what? Say I need to connect a joystick or something external through the Br, where do I find information on what pins are what? Also, if i do not specify what voltage a pin is, does it default to any voltage? Thank you for helping, Sorry if I am being a burden with all of my questions.
I’m a bit confused by why you need this for LEDs? Can you explain your initial issue a bit more? The outputs on the FPGA are push pull so unless you have an inout, input, or explicitly setting the output to z, using pulldowns doesn’t make sense.
Labs V2 doesn’t directly support XDC files yet (next feature to be added).
Your .acf should look like
clock clk CLOCK 100MHz
pin usb_rx USB_RX
pin usb_tx USB_TX
pin rst_n RESET
pin led[0] LED0 PULLDOWN
pin led[1] LED1 PULLDOWN
pin led[2] LED2 PULLDOWN
pin led[3] LED3 PULLDOWN
pin led[4] LED4 PULLDOWN
pin led[5] LED5 PULLDOWN
pin led[6] LED6 PULLDOWN
pin led[7] LED7 PULLDOWN
But again, this doesn’t make sense since led is an output unless you’re specifically setting it to z (which I’m not sure why you would for an LED).
If you’re using ACF files, then the names are the bank pins. If you’re using the Br, see this pinout guide. If you connected something to bank A pin 14, you would use the pin name of A14.
The ACF files will map the Alchitry names to the FPGA pin names. The mapping can be found here.
Note that special signals on the board have their own names. Like LED0 is the pin name for the first LED.
The voltage on all the IO is 3.3V with the exception of the dual voltage pins on the Au. These can be toggled to 1.8V by connecting VBSEL to 1.8V on bank D. If you do this but still connect 3.3V to any of the pins, you will likely damage the FPGA. (also note the new boards are 2.5V instead of 1.8V)
Just doing some projects for leds as a start to alchitry. I am new, so if i make obvious mistakes, there is probably no deeper meaning to it. Thank you for the .acf though 
No worries! If you end up with weird behavior, feel free to post your code/project and I can take a look.