Has anyone built the neorv32 core for the Alchitry AU boards?
Just wondering if there are any “gotchas” I need to be aware of.
I found this project that does the core + many peripherals in a SoC-like bundle :
They provide it as a ready-to-use VHDL, auto-converted Verilog and also as a ready-to-use Vivado IP block.
All of which seems to be fully customizable.
They offer demo Vivado project for Arty boards, I looked into the project file and I didn’t saw any board-specific stuff that would prevent us to use it on Alchitry.
I may give it a try when I get some free time 
I did manage to get it to work after a bit of faffing around, however I can’t seem to get the memory interface as I wanted to add some memory mapped custom bits to it.
The base one took up just under 1000LUTs, I added multiply and divide and it went to 1400LUTs still pretty good.
now if I can just get that memory out.
Oh, nice
I saw this example design where they externalized memory through the XBUS (Wishbone/AXI) :
The odcumentation states that the XBUS is memory-mapped in the CPU adress space so everything connecter to it can be accessed with load/store :
More details : [Datasheet] The NEORV32 RISC-V Processor
Thanks, I haven’t quite got my head around the who AXI thing yet, it’s something I’ll tinker with
300 MHz? 
Nice!
The project claims only 130 MHz on Cyclone IV, did I missed something? XD
There is a led blink sample provided, the bootloader offers an upload feature to load binary code, but I don’t know which terminal format is expected.
I couldn’t find the blink sample, when I looked in the repo it just had the main.c and makefile. Could you point me at it please?
They provide it as source code because since you can customise the instruction set and memory map, they can’t make a binary that would work with every customization.
So they expect you to make your own binaries using the provided toolchain : Software Toolchain Setup
Yeah sadly I’m using windows for the moment and those are for Linux.
That’ll change in a month though as I plan to switch to linux.
The toolchain exists precompiled for windows : https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v14.2.0-3/xpack-riscv-none-elf-gcc-14.2.0-3-win32-x64.zip
It’s the one recommanded by NEORV32 :
If you need Windows and Linux you can give WSL a try, it’s a very thin, tightly integrated and lightweight VM that allows to run a full linux distro within windows
I built the LED blinking demo and ran it on my Au v1
I can barely get above 100 MHz on my v1, so you probably have a v2?
Here it is if you wish to try it :
neorv32_led_exemple.zip (759 Bytes)
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that was 200MHz, rebuilding now with 300MHz.
Failed at 300MHz, my mistake…
Runs at 200MHz, Here’s the bitstream
design_1_wrapper.zip (67.7 KB)
Yes the example is a simple binary counter
I could do 200 MHz with timing failure (around -2ns WNS) but it seems to run properly.
I tried 300 MHz and it seems to start bootloader (the LED 0 lights up) but it stops before anything gets to the console.
Same with me, though if I bash the reset key sometimes I’d get a few characters.
The Au v2 and Pt have faster FPGA so maybe we could reach 300 MHz on these, I’ll try when I get my Pt.
I’m fiddling with the bootloader right now and I could configure it to make the UART much faster.
I mean… MUCH faster.
Like… 48x faster 
Went from 19200 to 921600 
The upload is now instant!
This is software controlled so you have to set it and recompile the bootloader, and you have to do the same in the app code since the app sets the UART speed too.
EDIT : Just tried 4800000 and it works too, 250x faster than default
Fasted I reached : 6144000, that’s 320x default 
Ok, switched to linux and built the tool chain AND built the example, had to modify the makefile to point to the correct compiler, and I uploaded the led test!!
However, I’m now stuck with a choice of using EITHER the Alchitry Loader OR a serial port 
(I’ve posted a thread about that)