Hi, I would like to ask when will be available schematic and ready for ship, please?
The product pages are kept up to date with ETAs. The Pt is still being laid out so the pinout is expected to change.
I just looked into the schematics of the Pt board. The pin VREFN_0 of the FPGA is not connected to AGND but to the temporary net N$61. Are the schematics not up to date or is this an error? I’m always using an external reference in my projects.
Wow excellent catch. That is indeed a mistake… It seems like it was from an import bug when moving the design from Fusion to Altium. You hopefully caught it in time for it to be fixed on the outer layer (I believe only the inner layers have been fab’d so far). If not, there’s a via on the AREF_N pin and I’ll connect it to AGND with a 0ohm resistor for this first batch (they’re right next to each other).
Either way, it’ll be fixed. I really appreciate the report.