VHDL to Verilog Conversion


does anyone know a good VHDL to Verilog converter?

I am using the Alchitry Cu with icestorm/nextpnr. And as yosys only works with Verilog I can not apply my VHDL knowledge.

I currently write stuff in Verilog but it is not my language of choice :wink:

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Update: I found this nice piece of software (seems very experimental now): https://github.com/ghdl/ghdl-yosys-plugin

I will try it in the next days.

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UPDATE: I wrote a quick LED counter to test and It works fine:

USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY alchitry_led IS
PORT (clk : IN std_logic;
usb_rx : IN std_logic;
usb_tx : OUT std_logic;
led : OUT std_logic_vector (7 DOWNTO 0));
END alchitry_led;

ARCHITECTURE alchitry_led_behav OF alchitry_led IS
SIGNAL clk_div : unsigned (31 DOWNTO 0);
SIGNAL cnt : unsigned (7 DOWNTO 0);
SIGNAL div : std_logic;

led <= std_logic_vector(cnt);
div <= std_logic(clk_div(24));
usb_tx <= usb_rx;

    PROCESS (clk)

            IF clk'EVENT AND clk = '1' THEN
                    clk_div <= clk_div + 1;
            END IF;

    PROCESS (div)

            IF div'EVENT AND div = '1' THEN
                    cnt <= cnt + 1;
            END IF;

END alchitry_led_behav;[/code]

I will further try if I can use the PLL etc. directly from VHDL. If there is demand I am now able to write a HowTo (I don’t know if anyone else wants to use Icestorm with VHDL :wink: ).

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