Verilog Tutorial - SPI


I am confused about why it seems like the same FIFO or buffer, data_d/data_q, is being used for both MISO and MOSI communication. On the rising edges of the SPI clock, data_d is reading bits in from MOSI. On the falling edges, these bits are being output on MISO. I would think each would have its own FIFO to read data in and data out from the slave device. Let me know if I am incorrect in assuming this buffer is considered a FIFO.

Also, why is it necessary to output the MSB to MISO when the SS signal is not pulled low?

Thanks in advance!

Can you link to the tutorial you’re using, Anieng?

Sure, here it is:

Thanks for the reply!

[color=#666666]Sure, here it is:[/color]


[color=#666666]Thanks for the reply![/color]

The data_d/_q flip flops aren’t really a FIFO but rather a shift register. The bits are shifted out as new bits are shifted in so after eight cycles, all eight bits will have shifted out with eight new bits (the received data) shifted in.

You could use two different sets of flip-flops but this is more efficient.

Note that this module assumes CPOL=CPHA=1. Other versions of SPI won’t work without modifications.