Oh cool, thanks for that tip, I’ll try that soon. Are there other translation/limitations to consider to port the SV code to V fully? I noticed some name translation related to the fakePullUp and reset_conditioner logic modules provided by the Alchitry toolchain to allow for developing on the IO Board w/ Cu. For example, before the respective definition brackets ({) of the reset_conditioner module and it’s references within the Alchitry_top file, there is a pound (#) sign found in front of the character, and I don’t have any clue as to its purpose or significance, if any.
I understand the reset_conditioner Alchitry provides for the Cu basically seems to be a 4-level D-Flipflop which (I think, IIRC) is configured as negative clock-edge triggered in conjunction with a reset-low signal, but I’m a little rusty at implementing multilevel D-flips from scratch since I haven’t done college-level Verilog since my ECE courses in like 2019, so if I could viably convert what’s been provided that would be of great assistance for pushing me forward on basic I/O practice work in this environment. I’m interested in retro gaming hardware restoration so Verilog is more likely than Lucid to be the accepted standard for open-source/hardware-compatible builds between collaborators.
If you’re getting .xdc files, your project is not for the Cu. There currently isn’t a way to change the target board for a project and you can only select this at the beginning.
Make a new project and make sure you select the Cu in the dialog.
You can get Verilog only files by selecting the open source toolchain as they don’t support SystemVerilog like iceCube2 does.
I was able to create a new project in Alchitry Labs V2 targeting the Cu, hit build, create a new iCEcube2 project in their GUI, import all the constraint (.pcf and .sdc) and source files (.sv) by changing the file filter to all.
Ok, well I managed to get the proper merged_constraints only after I changed the Labs V2 Toolchain from Yosys to IceCube2 and linked it to my IC2 install directory before rebuilding. That gave me the PCF and SDC that you mentioned. You were right about the design-file import filter - that and the double-click/button-select nature of the IC2 interface gave me the impression I wasn’t able to import the SV files at all, but after importing them filterless as you specified, the Synthesis now succeeds when I run it. Thank you so much, sorry for the config confusion.
EDIT: Importing output bin from IC2 into Alchitry Loader. After clicking Program, the AL successfully programmed the output bin into my Cu and the same logic circuit works perfectly fine! Awesome! Thanks folks
