Starting with Alchitry Au+

Hello there! I’ m trying to use the Alchitry Au+, with the Alchitry Ft element board to build a system that could receive data from an external ADC from the Usb 3.0 port of the Ft board.
I’ m quite new to the world of the FPGAs, so I’ m looking for advice if you have, in particular on how to adapt the Mojo tutorials also for Alchitry Au+, beacuse I saw that most of the tutorials are on the Mojo board. If you have suggestions about how to interface the Au+ with the ADC, are welcome, or also tips of any tipe.
Thank you!

I’d start by running through the beginner tutorials so you get a feel for hardware design. It’ll make understanding everything else much easier.

The Au+ is basically just the Au with a bigger FPGA so all the Au tutorials are identical except for choosing the Au+ from the board dropdown when you create your project.

While it isn’t included in the currently published Alchitry Labs version, you can download a module for talking to the FT600 here and the accompanying constraint file

I’ll have a tutorial for these shortly after they are in the published Alchitry Labs. Once you get a feel for Ludid, they should be pretty straightforward to use though.

I have tried to use the Ft600 module and the constraint file,that you attached here, with this simple top module that sends an ‘H’ to the usb port , but it seems to do nothing. The building is ok, but as I told you, when i program the configuration on the board it doesn’t send anything. Where can be the problem?
Here I attach the verilog top module:

module au_plus_top(
input clk, // 100MHz clock
input ft_clk,
input rst_n, // reset button (active low)
//output [7:0] led, // 8 user controllable LEDs
//input usb_rx, // USB->Serial input
//output usb_tx, // USB->Serial output
input ft_rxf, // RX buffer empty (1 = empty, 0 = not empty)
input ft_txe, // TX buffer full (1 = full, 0 = has space)
inout [1:0] ft_be, // bidirectional byte enable (1 = valid)
output ft_rd, // read flag (1 = inactive, 0 = read)
output ft_wr, // write flag (1 = inactive, 0 = write)
output ft_oe, // output enable (1 = FPGA output, 0 = FT600 output)
inout [15:0] ft_data // bidirectional data bus,

wire rst= !rst_n;
wire [15:0] data_out = 0;
wire [1:0] valid_dout= 0;
reg [15:0] data_to_send=0;
wire [1:0] valid_d_send=0;
wire FIFO_full=0;


// The reset conditioner is used to synchronize the reset signal to the FPGA
// clock. This ensures the entire FPGA comes out of reset at the same time.
//reset_conditioner reset_conditioner(.clk(clk), .in(!rst_n), .out(rst));

ft600 ft600

// assign led = 8’h00; // turn LEDs off

// assign usb_tx = usb_rx; // echo the serial data

assign valid_d_send= 2’b11;

always  @(posedge clk)

data_to_send = 16'h48;// Sending letter H (ASCII code) to usb 3.0 port


If you have it, the tutorial you mentioned, it would be very useful to me. Even tough if is a Beta version, I can test it and give you a feedback.

Does anyone have any other idea? Or has tried to use Alchitry Ft and can help me with USB 3.0 communication…