Reading analog inputs with the Alchitry Au

Are there any examples of how to use the Alchitry Au with analog inputs ?

The short answer is it’s kind of complicated. I document the process at some level in the XADC section of these notes

There’s an example project at the bottom called XADC_read_MUX which continuously reads and displays either
the dedicated analog input or one of several internal voltages, based on DIP settings. The usage
is described in the header of the au_top.v file.


I actually got to play around with this recently when updating our code for the Au (formerly I was using the MojoV3). I should mention that I got some pretty good kick start there from Alchitry.

Disclaimer: I briefly tested the code and it seemed to work but I could only test high vs low analog input (max ~ 1 V). Since then I just changed removed the vp/vn channel and inverted the addresses order, which I believe should not have any influence. Yet, I haven’t found the time to go back to that. On another note, I have no background in electronics, so everything is a bit of trials and errors for me. There are good chances I am not doing things the proper way.

How to set-up the XADC for the Au:

  1. In your project, open the Vivado IP catalog (under the Project menu item).
  2. In Vivado, in the “Vivado Repository” list, select “FPGA Features and Design” and double click on the item under “XADC”.
  3. In the newly opened window, select “Channel sequencer” under “Startup Channel Selection”.
  4. In the “Channel Sequencer” tab, select the following channels:
    vauxp4, vauxp5, vauxp6, vauxp7, vauxp12, vauxp13, vauxp14 and vauxp15 (see why below)
  5. Click “OK” and “generate” the core.
  6. Once Vivado is done generating the core (bottom of the main Vivado window, there should be a “progress” that is green and 100% when it is done), close Vivado. In Alchitry, the new core should have been detected and should have appeared in the project.

According to the Au schematic (linked on the Au page), these channels are the one connected to a Br shield pin. The others seem to be connected to the DDR3. They are all on bank 35 (see the .xlsx file joined to this post).

How to read the analog channels (Lucid):
Based on what Alchitry sent me for reading the dedicated vp/vn, I put together a module in our code and briefly tested it. I just pushed the code now to Github. What to look at:

  • In Constraints: xadc.xdc. In this file, you have the pin declarations of each analog input to the top module. These are called “physical pins” in the .xlsx I attached to this post. I apologize for the confusing renaming of each input as vp#/vn# with an arbitrary number.
  • In Source: au_top.luc. The top module inputs (defined in xadc.xdc) are connected to an instance of the “analog” module.
  • In Source: analog.luc. The module inputs are mapped to the xadc inputs. Then the channels are read one after the other each time the XADC has performed a conversion. The addresses are connected to the xadc by a counter traversing an array, these were found in the XADC manual.

Use the .xlsx to determine to which Br pins each channel corresponds.

BTW, I didn’t manage to get the dedicated Vp/Vn channel to work this way…

Hope it helps!


Related to the topic of reading analog inputs with the Au, it seems I can only measure voltage up to 1 V (at which point the 16 bits max out), and not 1.8 V. Is this expected?


The 7 series FPGA have 12-bit ADCs, and yes the unipolar range is 0-1V. The bipolar range is -0.5 - +0.5 V.

Oh yeah I see it now in the manual. Thanks !