Passing variables into case statements

I thought I found an answer - wrong. I tried making a var testbyte and then tying it to, but that did not work either. How do I get a byte from rx_uart into a case(state.q) in au_top_plus.luc? It’s the case structure from DDR3 tutorial.

error produced in Alchitry Labs:
Bin file (C:\Users\howdy\Documents\Alchitry\Xilinx\DDR_Test\work\vivado\DDR_Test\DDR_Test.runs\impl_1\au_plus_top_0.bin) could not be found! The build probably failed.

This is a standard error when something is wrong, and “No errors detected” when checking.

This is the error in Vivado:
[Synth 8-1749] cannot have packed dimensions of type integer [“C:/Users/howdy/Documents/Alchitry/Xilinx/DDR_Test/work/vivado/DDR_Test/DDR_Test.srcs/sources_1/imports/verilog/au_plus_top_0.v”:163]

This is what I tried:
var testbyte[8];

always {
/* Clock Wizard Connections */
clk_wiz.clk_in1 = clk; // 100MHz in
clk_wiz.reset = !rst_n; // reset signal

rx.rx = usb_rx;         // connect rx input
usb_tx = tx.tx;         // connect tx output

rx1.rx = dcs_rx;

// dcs_tx = tx1.tx;

then near the case:

testbyte =; // is from a second uart, the original is still used as USB_RX

case (state.q) {
mig.mem_in.wr_en = 1;
mig.mem_in.wr_data = testbyte; //trying to use this var to transfer received byte from uart_rx1. Using here does nothing but I do not get any errors.
if (mig.mem_out.wr_rdy)
state.d = state.WRITE_CMD;

If I do not specify size of var testbyte[8]; and just say var testbyte; I get this warning from Lucid:

Line 78, Column 15 : The signal "" is wider than "testbyte" and the most significant bits will be dropped