Mojo V3 Lucid Sdram Test Wrong

Legacy Posts General Questions
1

I made the shield to test the sdram, I used the same components used to build the original.

Then I ran the SDram test in Lucid and I continue to detect output errors shown by the configuration of the LEDs on the board: LEDs 6: 0 on and 7 flashing.

So I tried to use the example in verilog under ise project navigator and with the latter the test works, 7 LEDs off and one flashing.

There must be some problem with the lucid project but I couldn’t identify it.

Can someone try to do the sdram test on mojo V3 with Lucid
to identify the problem?

Thank you

2

I observed differences between the sdram test project compared to the description in the tutorial.
And precisely in the parts:

[code]// The OODR2 is used to output the FPGA clock to
// an output pin because a clock can’t be directly
// routed as an output.
xil_ODDR2 oddr (
#DDR_ALIGNMENT (“NONE”),
#INIT (0),
#SRTYPE (“SYNC”)
);

// The IODELAY2 is used to delay the clock a bit
// in order to align the data with the clock edge.
// These settings assume a 100MHz clock and the
// SDRAM Shield being stacked next to the Mojo.
xil_IODELAY2 iodelay (
#IDELAY_VALUE (0),
#IDELAY_MODE (“NORMAL”),
#ODELAY_VALUE (ODELAY_VALUE),
#IDELAY_TYPE (“FIXED”),
#DELAY_SRC (“ODATAIN”),
#DATA_RATE (“DDR”)
);[/code]

and in the parameters passed to these directives.

[code]// Connections for the IODELAY2
iodelay.ODATAIN = oddr.Q; // use the ODDR2 output as the source
iodelay.IDATAIN = 0;
iodelay.T = 0;
iodelay.CAL = 0;
iodelay.IOCLK0 = clk;
iodelay.IOCLK1 = ~ clk;
iodelay.CLK = clk;
iodelay.INC = 0;
iodelay.CE = 0;
iodelay.RST = 0;

// Connections for the ODDR2
oddr.C0 = clk;
oddr.C1 = ~ clk;
oddr.CE = 1;
oddr.D0 = 0; // using 0 for D0 and 1 for D1 inverts the clock
oddr.D1 = 1; // because D0 is output on the rising edge of C0
oddr.R = 0;
oddr.S = 0;[/code]

These are the ones in the tutorial:

[code]// The OODR2 is used to output the FPGA clock to
// an output pin because a clock can’t be directly
// routed as an output.
xil_ODDR2 oddr (
#DDR_ALIGNMENT (“NONE”),
#INIT (0),
#SRTYPE (“SYNC”)
);

// The IODELAY2 is used to delay the clock a bit
// in order to align the data with the clock edge.
// These settings assume a 100MHz clock and the
// SDRAM Shield being stacked next to the Mojo.
xil_IODELAY2 iodelay (
#IDELAY_VALUE (0),
#IDELAY_MODE (“NORMAL”),
#ODELAY_VALUE (100),
#IDELAY_TYPE (“FIXED”),
#DELAY_SRC (“ODATAIN”),
#DATA_RATE (“SDR”)
);

// Connections for the IODELAY2
iodelay.ODATAIN = oddr.Q; // use the ODDR2 output as the source
iodelay.IDATAIN = 0;
iodelay.T = 0;
iodelay.CAL = 0;
iodelay.IOCLK0 = 0;
iodelay.IOCLK1 = 0;
iodelay.CLK = 0;
iodelay.INC = 0;
iodelay.CE = 0;
iodelay.RST = 0;

// Connections for the ODDR2
oddr.C0 = clk;
oddr.C1 = ~ clk;
oddr.CE = 1;
oddr.D0 = 0; // using 0 for D0 and 1 for D1 inverts the clock
oddr.D1 = 1; // because D0 is output on the rising edge of C0
oddr.R = 0;
oddr.S = 0;[/code]

Which are the correct ones?
[hr]
I built the project with mojo IDE 1.3.6 and the leds behave correctly all off except one flashing.

There is something wrong when compiling build test project in Alchitry. :smiley: :smiley: :smiley: