Increasing IO with SPI using the Au and Br

Legacy Posts General Questions
1

I’m currently developing an application with the Au and Br using Alchitry Labs v1.1.6 in
Lucid, however I need many more switching outputs, so serial I/O expansion is needed.

The switching speed requirement is very high so SPI is my prefered choice and the
MCP23S17 16-Bit SPI Expander with serial interface is ideal for the application for
extending multiple GPIOs.

I’m asking for SPI implementation tips for the Au and Br as the current tutorial is
written for the Mojo, and I’m not sure how to use the spi_master compontent in
Alchitry Labs, or to add the SPI I/O to a constraints file.

Also is there a Br constraints file for the Au?

Thanks in advance,

Mick

2

Based on the following link;

https://github.com/alchitry/Alchitry-Labs/blob/master/src/com/alchitry/labs/hardware/pinout/AlchitryAuPinConverter.java

I have created a new constraint file called, au_br.acf wth the following two lines;

pin spi_ss SPI_SS;
pin spi_sck SPI_SCK;

and declared them as input and output respectively in the au_top.luc file

input spi_ss,
output spi_sck,

So far only the spi_ss can be used as the project will not build with spi_sck.

3

Hey Mick,

There isn’t a specific constraint file for the Br since you will want to define your own pinout. Just use the pin numbers in your .acf file that are on the board (ie A2 for bank A pin 2).

Can you share your code/error messages?

Justin

4

Hi Justin,

I’ve developed a really cool project and custom .acf loosely based on your wave project, however this one switches Fibonacci quantities of 21, 34, 55 and 89 PWM outputs using the Au and the Br.

Push buttons with 330 Ohm resistors on B27 and B28 changes the frequency and the waveform and offset respectively. Was interested in possibly going up to 144 using SPI, but still confused with Bank D 23, 24, 27 and 28 as SPI on the Au. Now working on a MOFSET H-bridge signal generator at 4.2kHz with the signal from the FPGA.

BTW those Adafruit 10 pin IDC breakout cables on the Br keep that many GPIO nice and tidy.

Mick
[hr]
working file: io.acf

pin rpp_pwm[0] B14; // Cable 1 I/O 0
pin rpp_pwm[1] B17; // Cable 1 I/O 1
pin rpp_pwm[2] B15; // Cable 1 I/O 2
pin rpp_pwm[3] B18; // Cable 1 I/O 3
pin rpp_pwm[4] B37; // Cable 1 I/O 4
pin rpp_pwm[5] B34; // Cable 1 I/O 5
pin rpp_pwm[6] B36; // Cable 1 I/O 6
pin rpp_pwm[7] B33; // Cable 1 I/O 7

pin rpp_pwm[8] B8; // Cable 2 I/O 0
pin rpp_pwm[9] B11; // Cable 2 I/O 1
pin rpp_pwm[10] B9; // Cable 2 I/O 2
pin rpp_pwm[11] B12; // Cable 2 I/O 3
pin rpp_pwm[12] B43; // Cable 2 I/O 4
pin rpp_pwm[13] B40; // Cable 2 I/O 5
pin rpp_pwm[14] B42; // Cable 2 I/O 6
pin rpp_pwm[15] B39; // Cable 2 I/O 7

pin rpp_pwm[16] B2; // Cable 3 I/O 0
pin rpp_pwm[17] B5; // Cable 3 I/O 1
pin rpp_pwm[18] B3; // Cable 3 I/O 2
pin rpp_pwm[19] B6; // Cable 3 I/O 3
pin rpp_pwm[20] B49; // Cable 3 I/O 4
pin rpp_pwm[21] B46; // Cable 3 I/O 5
pin rpp_pwm[22] B48; // Cable 3 I/O 6
pin rpp_pwm[23] B45; // Cable 3 I/O 7

pin rpp_pwm[24] A20; // Cable 4 I/O 0
pin rpp_pwm[25] A23; // Cable 4 I/O 1
pin rpp_pwm[26] A21; // Cable 4 I/O 2
pin rpp_pwm[27] A24; // Cable 4 I/O 3
pin rpp_pwm[28] A31; // Cable 4 I/O 4
pin rpp_pwm[29] A28; // Cable 4 I/O 5
pin rpp_pwm[30] A30; // Cable 4 I/O 6
pin rpp_pwm[31] A27; // Cable 4 I/O 7

pin rpp_pwm[32] A14; // Cable 5 I/O 0
pin rpp_pwm[33] A17; // Cable 5 I/O 1
pin rpp_pwm[34] A15; // Cable 5 I/O 2
pin rpp_pwm[35] A18; // Cable 5 I/O 3
pin rpp_pwm[36] A37; // Cable 5 I/O 4
pin rpp_pwm[37] A34; // Cable 5 I/O 5
pin rpp_pwm[38] A36; // Cable 5 I/O 6
pin rpp_pwm[39] A33; // Cable 5 I/O 7

pin rpp_pwm[40] A8; // Cable 6 I/O 0
pin rpp_pwm[41] A11; // Cable 6 I/O 1
pin rpp_pwm[42] A9; // Cable 6 I/O 2
pin rpp_pwm[43] A12; // Cable 6 I/O 3
pin rpp_pwm[44] A43; // Cable 6 I/O 4
pin rpp_pwm[45] A40; // Cable 6 I/O 5
pin rpp_pwm[46] A42; // Cable 6 I/O 6
pin rpp_pwm[47] A39; // Cable 6 I/O 7

pin rpp_pwm[48] A2; // Cable 7 I/O 0
pin rpp_pwm[49] A5; // Cable 7 I/O 1
pin rpp_pwm[50] A3; // Cable 7 I/O 2
pin rpp_pwm[51] A6; // Cable 7 I/O 3
pin rpp_pwm[52] A49; // Cable 7 I/O 4
pin rpp_pwm[53] A46; // Cable 7 I/O 5
pin rpp_pwm[54] A48; // Cable 7 I/O 6
pin rpp_pwm[55] A45; // Cable 7 I/O 0

pin rpp_pwm[56] C46; // Cable 8 I/O 0
pin rpp_pwm[57] C49; // Cable 8 I/O 1
pin rpp_pwm[58] C45; // Cable 8 I/O 2
pin rpp_pwm[59] C48; // Cable 8 I/O 3
pin rpp_pwm[60] C5; // Cable 8 I/O 4
pin rpp_pwm[61] C2; // Cable 8 I/O 5
pin rpp_pwm[62] C6; // Cable 8 I/O 6
pin rpp_pwm[63] C3; // Cable 8 I/O 7

pin rpp_pwm[64] C9; // Cable 9 I/O 0
pin rpp_pwm[65] C12; // Cable 9 I/O 1
pin rpp_pwm[66] C8; // Cable 9 I/O 2
pin rpp_pwm[67] C11; // Cable 9 I/O 3
pin rpp_pwm[68] C42; // Cable 9 I/O 4
pin rpp_pwm[69] C39; // Cable 9 I/O 5
pin rpp_pwm[70] C43; // Cable 9 I/O 6
pin rpp_pwm[71] C40; // Cable 9 I/O 7

pin rpp_pwm[72] C15; // Cable 10 I/O 0
pin rpp_pwm[73] C18; // Cable 10 I/O 1
pin rpp_pwm[74] C14; // Cable 10 I/O 2
pin rpp_pwm[75] C17; // Cable 10 I/O 3
pin rpp_pwm[76] C36; // Cable 10 I/O 4
pin rpp_pwm[77] C33; // Cable 10 I/O 5
pin rpp_pwm[78] C37; // Cable 10 I/O 6
pin rpp_pwm[79] C34; // Cable 10 I/O 7

pin rpp_pwm[80] C21; // Cable 11 I/O 0
pin rpp_pwm[81] C24; // Cable 11 I/O 1
pin rpp_pwm[82] C20; // Cable 11 I/O 2
pin rpp_pwm[83] C23; // Cable 11 I/O 3
pin rpp_pwm[84] C30; // Cable 11 I/O 4
pin rpp_pwm[85] C27; // Cable 11 I/O 5
pin rpp_pwm[86] C31; // Cable 11 I/O 6
pin rpp_pwm[87] C28; // Cable 11 I/O 7

pin rpp_pwm[88] B23; // Cable 12 I/O 0
pin mmr_pwm[0] B20; // Cable 12 I/O 1
pin mmr_pwm[1] B21; // Cable 12 I/O 2
pin mmr_pwm[2] B31; // Cable 12 I/O 3
pin mmr_pwm[3] B30; // Cable 12 I/O 4

pin io_button[0] B28 pulldown;
pin io_button[1] B27 pulldown;
pin io_button[2] B24 pulldown;
[hr]
excerpt from file: au_top

module au_top(
input clk, // 100Mhz clock
input rst_n, // reset button (active low)
output reg [7:0] led, // 8 user controllable LEDs
input usb_rx, // USB->Serial input
output reg usb_tx, // USB->Serial output
output reg [88:0] rpp_pwm, // RPP Pulse Width Modulation Outputs
output reg [3:0] mmr_pwm, // MMR Wireless Transfer Pulse Width Modulation Outputs
inout [2:0] io_button // 3 push buttons
);

This program is working fine with the above .acf, but adding SPI on the Au with the Br would be a bonus.

5

So the “SPI” pins on bank D are on the Cu only. These aren’t really for using SPI in your project and connect to the SPI flash memory that is used to hold the FPGA’s configuration. You can access them in your design to read the flash memory if you really want to. It’s possible to use the extra space for stuff.

On the Au, these pins are the JTAG pins.

If you want to use SPI in your project, just select any four IO pins that are convenient and use those. The magic with FPGAs is that there are almost no special IO pins except for access to special routing resources like global and bank routes for clocks and resets.