To do this, with an Au project open go to Project → Vivado IP Catalog.
Wait a little for the catalog to open.
Navigate to FPGA Features and Design → Clocking → double click Clocking Wizard
You can now go through the wizard to setup the PLL.
Things to note, you can’t use the main clock if you are also using the PLL. The routing in the FPGA can’t route it to the general fabric and the PLL. To get around this, if you still need 100MHz, you can make the PLL output multiple frequencies including 100MHz.
The default clock input is 100MHz which is perfect.
You should only really need to mess with the “Output Clocks” tab and maybe “Port Renaming” if you want to change that. I usually name the clock outputs to clk_MHZ where MHZ is the frequency so like clk_200.
Once you’re done with the wizard you’ll be prompted to generate the output products. Click Generate.
On the bottom of the window you’ll see it’s progress. DON’T CLOSE THE WINDOW YET. You must wait for the synthesis to finish.
Once it shows 100% under “Progress” (shouldn’t take very long) you can close the window.
Alchitry labs then scans for new cores. They should show up in the project tree. You should see a clk_wiz_0 core and a clk_wiz_0_stub.v file under it.
The stub file is the “black box” version of the core and is useful to look at to know what the ports are named.
If you didn’t change much in the wizard, you should have a clock and reset input and a clock and locked output.
You may want to set the reset input connect to the reset button and use the locked output for the rest of your designs reset (inverted so it is reset when not locked). This will ensure a stable clock.
Use the clock output as you would any other clock.