General question (HDMI shield + Software question)

Hi all,

I was intrigued by the nice design and possible extensions of this new FGPA board.
I have 2 questions before I commit into buying this board (first the CU to get myself familiar with the setup).

  1. Is the development software free to use with no ristrictions (eg no hidden fees or costs)?
  2. Is a HDMI (with embedded audio) or VGA + external audio-out shield available for the Alchitry CU board?

I hope to hear from someone, thx so much in advance,

Jeroen Ensing
from Sneek, The Netherlands

Hey Jeroen,
To answer your questions:

  1. Yes - but to elaborate - The Cu uses an open-source toolchain, so that will obviously be without cost. The Au uses Xilinx Vivado, provided by the FPGA’s manufacturer. This is free to use, although there are extraordinarily expensive enterprise editions (which you won’t need) available. Note, I have never used the Cu myself. Software provided by Alchitry is also free - Alchitry Labs (full IDE), and Alchity Loader (put .bin’s onto the board), are also open-source (if I remember correctly).

  2. There are no video display shields available as of yet, although I imagine you could make your own VGA interface with some external components using the Br element.

Hope that helps.

Hi Mark, super, thx for your extensive answers.

Looks like the CU is a nice board to test things out.
My first FPGA experience was a website from Nandland.

I saw you are a moderator, so you prob. looked at many, many posts in this forum :wink: Have you noticed someone to use the CU board to build a low-power (8 bit / 16 bit) retro gameing (C64/NES/Amiga/SNES) handheld machine? I’m also eager to find out if someone has accomplished a working HMDI out (+ embedded audio) with the use of a custom PCB (HDMI is a little picky concerning timing and PCB lane lengths ;))

If I want to use this FPGA I prob. gonna use it in combination with a IPS display (RGB, 40 pin FPC)
So this is also an option for me (I look forward into design the PCB or altering the BR PCB design ;).

p.s. the CU / AU / AU+ uses different FPGA’s.
A real important factor (next to LUT’s ;)) is the amount of Block RAM inside the FPGA.
Am i correct that these are the values:

  • CU > Lattice iCE40 HX8K > 128 kB = 16 KB
  • AU > Xilinx Artix 7 XC7A35T > 50x 36Kb = 1800 Kb = 225 KB
  • AU+ > Xilinx Artix 7 XC7A100T > 135x 36Kb = 4860 Kb = 607,5 KB

So am I correct in my assumption, to run an Amiga 500 (RAM = 512 KB) game, the AU+ is sufficient, also for a nice overhead for the video buffer?
is SNES more-or-less the same?

Jeroen Ensing

Happy to help!
I have watched a fair bit of nandland videos, it’s a shame he stopped posting frequently - glad to hear the go board is a good product.
Honestly, I don’t know a whole lot about this stuff - I just purge the spammers, approve posts, and answer the questions I can. I can’t say I have noticed any retro gaming posts on any of the three boards as of yet. Most of the posts are concerning hardware/software issues, but if you want to check out the “show and tell” category in the forum, you might find something (a brief search for SNES returned only this thread, I think you are out of luck).

I know there is an (incomplete) GPU tutorial, where Justin walks you through designing a GPU to render a 3d model, and send that to a little display over some non-consumer-grade protocol, directly wired to an Au. Probably not super helpful, just putting that on your radar. I think the HDMI element has been “coming soon” for quite a while now, so hopefully it will be released soon. Justin, if you read this - any updates?

As for the amount of RAM in the FPGA’s-
As I’m sure you know, the Au+ is EXPENSIVE - see if you can make use of the 256mb of DDR3 on the Au - which you probably already know about, but I dont want you to spend another $200 on the Au+ just to realize it is complete overkill. I understand you can also get another 400Kb of distributed ram out of the Au, should that be useful. Souce:

Based on Wikipedia, the SNES has a total of 192KB of RAM (128 general purpose, 64 audio + video) - although the SNES’s CPU runs an order of magnitude faster than the Au clock. As you know your project (and FPGA’s) better than I do, I won’t make any claims as to whether a product I do not fully understand will suit your needs - but the numbers you found appear correct based on my reading of the Xilinx datasheets.

This sounds like a super cool project - I would love it if you kept me and the forum updated on any progress!

Hi Mark, thx so much for your extensive answer and information.
I appriciate it a lot :slight_smile:
I am puzzled by two things concerning RAM and one thing consering clock speeds, perhaps you (or someone of the community) can help me out (one more time ;))?

The Amiga System (the most demanding core I want to ‘emulate’) uses 512KB RAM,
So to run games I need to have direct access to 512KB RAM or more.

My initials thought was to use the Xilinx Artix 7 XCA7A100T (135 x 36kB = 4860 kb = 607,5 KB Block RAM) as the heart of my handheld system (a nice but expensive handheld system ;)) My 3 questions are:

1.) The XCA7A100T has a 1188 Kb (= 148,5KB) Maximum Distributed RAM, is this a problem for me since the Amiga core nees 512KB at once?
2.) If I choose the AU board (way more wallet fiendly, but: [color=#888888]Xilinx Artix 7 XC7A35T > 50x 36Kb = 1800 Kb = 225 KB Block RAM[/color]); how can I ‘transfer’ or make use of the DDR3 memory (where there is plenty off) for direct access for the FPGA, so the Amiga Core sees this as 512KB+ RAM?
3.) Is it possible to work with custom clock speed / crystals with for example the BR expansion board? thus ‘emulating’ the 4 different cores at their right speed?

Cheers, Jeroen

Glad I could help. After looking at the SNES and Amiga 500’s specs, these should both be within the capabilities of the AU.

1 & 2) The latency of the Amiga 500’s ram was 150ns (source:, which is far more than what you should get out of the DDR3 ram - at WORST ~20ns (source:, but I don’t think this counts memory controller latency. Either way, this will be far faster than the original Amiga 500. You should use the block ram akin to a CPU cache (don’t take my word for that, please double-check me), 255KB should be enough for such an early computer. Point is, the ram of the AU is more than sufficient. You should check out for information on the use of the AUs DDR3. The SNES also has ram in the kilobyte range, making the AU more than sufficient.

  1. The AU’s clock operates at 100mhz by default. While you can use an internal PLL to customize this, you shouldn’t need to. I was completely wrong prior to this, apologies. I believe I misread mhz as ghz, whoops. Both the Amiga 500 and SNES run in the megahertz range, far slower than the AU. Speed should not be an issue.

Point is, after a lot more reading, it seems AU has more than enough for anything you should need to do for the Amiga 500 or SNES, in terms of clock speeds, ram quantity and speed, and i/o.
During said reading, it appears as though someone has already made an FPGA implementation of the Amiga 500 - see Based on the FPGA used, which had around eight thousand logic elements, the AU’s 33 thousand should be enough. Note, there could be some other critical spec that your FPGA needs to fill, but as far as I can tell, all is good.

Happy to help,

Hi Mark, super, this all sounds very possitive :wink:

The ‘regular’ AU is also wallet friendly (well sort of ;))
P.s. instead of the Minimig there is another huge product out there, the MiSTer project:
it’s a super mature product (retro FPGA machine) and it has a huge community behind it (which is a major thing). This device is a little bulky and is not meant to be used as a handheld device (which would be my target/niche). But cores for all the major systems has already been written. It will be a challenge to ‘port’ these to the [color=#666666]Xilinx Artix 7 XC7A35T FPGA[/color] for the 4 cores (C64/NES/Amiga/SNES) I want to ‘emulate’.
There’s also another project out there: the Analoque Pocket, but this (pricey and delayed) device takes on another approach which is not the way I want to approch it:

Super you provided the url’s for the memory issues and work arround so the FPGA has access to it.
Also nice to hear clock speeds won’t be an issue.

Now it’s time for me (I guess) to start developing.
I will keep you and the community posted if I have any progress regarding this project, ok?
P.s. if you hear from Justin regarding an update about his GPU tuturial (perhaps via a 40-pin RGB connector in combination with an IPS display, or a HDMI output with embedded audio) I will be glad to hear more. I will also keep an eye out in this forum.

Thx for now and your time researching SNES and Amiga fact and figures.

Jeroen Ensing