FPGA as Logic Analizer & Forum Project

I have recently started working on such a project with the Alchitry Au.
I am total noob with FPGAs so progress is slow.
I have a working prototype that works with Sigrok Pulseview by emulating the Openbench Logic Sniffer/SUMP protocol.
It is using the DDR ram memory for capturing data and I tested a sampling rate of 10MHz with 8 channels so far and 1 million samples.
There are still quite a few problems with it.
In the example DDR project it states that the “UI” clock from the RAM should be used for the project which is 81.25 MHz, due to this the sampling rate is not dead on 10MHz.
Next I plan to find a solution for this clocking problem and to have configurable sampling rate and sampling depth from Pulseview. They are configurable in the project but only at compile time.