Using Alchitry Labs 1.0.3 on Linux using the ubuntu-provided IceStorm packages (fpga-icestorm et al).
I had the IDE create a new Lucid “Cu IO Element Demo” project and built it.
It fails with:
[code]…
Finished synthesis.
Project IceStorm doesn’t support .sdc constraints. “/home/…/CuDemo/work/constraint/alchitry.sdc” will be ignored.TBUF gate must drive top-level output or inout port
Finished placement.
Bin file (/home/…/CuDemo/work/alchitry.bin) could not be found! The build probably failed.[/code]
rrc
March 7, 2019, 2:01am
2
Did you check if all inputs and outputs are assigned correctly?
“fatal error: $TBUF gate must drive top-level output or inout port”
sounds like your .blif file wants to drive something the wrong way.
This is the default project shipped with the alchitry-labs IDE, so I would have expected it to work unchanged.
rrc
March 7, 2019, 1:58pm
4
Maybe this is the issue: https://github.com/YosysHQ/arachne-pnr/issues/112
What version of yosys and arachne-pnr are installed?
Sadly I cannot test as I don’t know how to pass lucid to yosys (Alchitry-Labs does not run on my machine). If you have the converted Verilog (*.v) I could test with my version.
Ubuntu 18.04
fpga-icestorm 0~20160913git266e758-3
[code]$ yosys -V
$ arachne-pnr -v
rrc
March 8, 2019, 1:07pm
6
I tried with different newer versions of yosys and arachne-pnr.
The result is the same:
On the 35C3 congress I heard that arachne-pnr is superseded by nextpnr so I tried to build with it. And it seems to be successful. I did not had the time to test. But there is an bitstream (see attachment (named .txt as else not accepted)).
What I did to build (In the work directory):
yosys -p 'synth_ice40 -top cu_top_0 -json alchitry.json' verilog/*.v
cat constraint/*.pcf > all.pcf
nextpnr-ice40 --hx8k --package cb132 --json alchitry.json --pcf all.pcf --asc alchitry.asc
icepack alchitry.asc alchitry.bin
The toolchain I had to compile by hand:https://github.com/YosysHQ/nextpnr https://github.com/cliffordwolf/icestorm https://github.com/YosysHQ/yosys
Sadly this is not a comfortable way for unexperienced users. As this toolchain is very new you have to expect some issues.
I will try the bitstream later (I hope there is something to see without the shield).
rrc
March 8, 2019, 6:03pm
7
As far as I can test with just the basic Cu board it worked. It wasn’t anything on the LEDs but the programmed loop of the serial bus responded.
I tested that with python:
[code]>>> from pylibftdi import Device;
device = Device(interface_select=2)
The IO example doesn’t build for me under IceStorm either although I get a different error during synthesis. I haven’t had a chance to figure out what’s going on.
It does build and work under IceCube.