AU Pin Mapping and Board FIles for Vivado

For better or worse I am determined to learn to use all of the Vivado tool suite. To that end I have created a set of board files that will add the Au board to Vivado’s set of available boards, so that I can use the block design tools.

To use: unzip the contents of the attached zip into: C:\Xilinx\Vivado\2019.1\data\boards\board_files\alchitry-au\1.0 (for windows users) and restart the Vivado gui.

Currently this includes components for: clock, reset, leds, uart, spi flash, DDR3 SDRAM, and GPIO Banks A-D.

GPIOs are implemented as interfaces on the FPGA. This looks like Vivado will treat this like a bus. I am undecided if I will leave it like this or re-implement as connectors.

At this point I can only confirm that Vivado will create a project from this and allow the creation of a block design with the aforementioned components. I have not yet tested any projects using this set of files yet.

While reasonable care was taken to get the pin mappings right, this was done late at night so YMMV. If you find an error, please let me know.

This was heavily modeled on (appropriated from) the Arty A7 board files.

Also attached is the spreadsheet I used to to generate the pin mapping entries for the pin file and the board file along with the Xilinx pinout. Hopefully I will have a master xdc file generated tomorrow.

Suggestions are welcome.

Have you found any good books (or Udemy courses) which provide a hands-on introduction to each of the tools in the Vivado Suite?

There is a course on Udemy called something like, Vivado From Top to Bottom. I have not taken it, but its on my list. It gets good reviews.

Have you generated the master xdc file yet? And have you successfully made a Vivado project with the Alchitry AU and then generate the bitstream and upload it to the board with the hardware manager?

I have tried and it does not work. :huh: