I’m having some problems running the “memory interface generator” in vivado.
I’m trying to configure the DDR3 basic on the schematic and XDC files, however I get an error;
ERROR : The port ddr3_addr[5] is allocated in the bank 15 where the input ports are allocated. Enable the Internal Vref to use the Vref as GPIO.
now I believe, I need these lines;
set_property INTERNAL_VREF 0.7 [get_iobanks 65]
set_property INTERNAL_VREF 0.84 [get_iobanks 67]
but with those in the projects XDC file and with the project built, I still get the error.
I’m using the Alchitry AU board and trying to get DDR turned on using the DDR tutorial. I have copied the entries for this .xdc file, but Vivado refuses to implement it because the MIG generator only allows (and specifies in the MIG documentation) that the Memory Voltage be set to 1.5V, not the 1.35V listed in this .xdc. The Memory Voltage option appears to be hardcoded (greyed out) at 1.5V.
I’m running the latest Vivado 2021.2 and alchitry lab version 1.27. Is anyone doing anything with DDR on this board? Looks like no DDR posts or updates for quite a while. I also run a design of my own in verilog and am running into the same problem, I’m unable to set the memory voltage to 1.35.