AU - DDR3 PIn use

I’m having some problems running the “memory interface generator” in vivado.
I’m trying to configure the DDR3 basic on the schematic and XDC files, however I get an error;

ERROR : The port ddr3_addr[5] is allocated in the bank 15 where the input ports are allocated. Enable the Internal Vref to use the Vref as GPIO.

now I believe, I need these lines;

set_property INTERNAL_VREF 0.7 [get_iobanks 65] set_property INTERNAL_VREF 0.84 [get_iobanks 67]
but with those in the projects XDC file and with the project built, I still get the error.

I’ve tried this thread -
But sadly the project that is created is blank and has no mig_7series_0 module.

Could you explain how to configure this to work please?

The easiest way to bypass all this is to use Alchitry Labs and choose Project->Add Memory Controller. This will automatically configure it correctly.

If you want to do this outside Alchitry Labs, you can download the mig project file here

You can use this with the Vivado IP Catalog to generate a MIG core.

You may also need the following pinout file when creating the core.

I’m using the Alchitry AU board and trying to get DDR turned on using the DDR tutorial. I have copied the entries for this .xdc file, but Vivado refuses to implement it because the MIG generator only allows (and specifies in the MIG documentation) that the Memory Voltage be set to 1.5V, not the 1.35V listed in this .xdc. The Memory Voltage option appears to be hardcoded (greyed out) at 1.5V.

I’m running the latest Vivado 2021.2 and alchitry lab version 1.27. Is anyone doing anything with DDR on this board? Looks like no DDR posts or updates for quite a while. I also run a design of my own in verilog and am running into the same problem, I’m unable to set the memory voltage to 1.35.

Try using the same Memory Part as the above project file : MT41K128M16XX-15E

Not all parts support different voltages.