Au clean Vivado project and xdc files related to built in components

Hi all,
I would like to created a project on Au in Vivado uses DDR3 and another built in component (flash) and looking for clean Vivado project or constrains xdc file included DDR3 and flash signals. There are only LEDs, USB and button in Au-Base-Project on the git repository.
Thanks a lot for help.

Hey Jan,

The easiest way to get the DDR memory controller setup is to install Alchitry Labs, create an Au project and go to “Project->Add Memory Controller”. Wait for the core to build then click the hammer icon to build your project.

Once the project is built, you can close Alchitry Labs.

In the project’s folder you’ll find a “work” folder. You can copy this to wherever you want and rename it. In the “work” folder, you will find a folder named “vivado” with another folder with the name of the project you made. In that folder is a Vivado project file you can open in Vivado and use however you want.

This project will have the default constraints added and the Verilog equivalents to the starter Lucid code.

It will also have the memory interface IP added and configured for the board.

The flash is only a few pins and shouldn’t be too difficult to create your own constraints file for them. I don’t have one premade as I don’t have any public examples for interfacing with it.

I’m using Au+ board and when I “Project->Add Memory Controller” it thinks I exited Vivado early and cannot find the ‘stub’ file! Is it because I am not using the plain Au board?

As long as your project is for the Au+, it should work. What version of Vivado do you have installed? It needs to be 2020.2 NOT 2020.3. 2020.3 was a weird release that only supports one type of FPGA and doesn’t support the Au/Au+