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Some confusion about Au DDR3 interface
#1
Hi - I'm trying to work out exactly how this is addressed, and something's wrong with my math.

Starting assumption - it's a 256MB part, and has a 28-bit address field - which is really a 25-bit field since the last 3 are reserved as 0s for ordering.  So there are 2**25 => 33,554,432 distinct addresses.  Which is each address was for an 8-byte block, that multiplies back to 256 MB - but the data in bus is 128-bits / 16 bytes wide?

Do these overlap?  Can I write to address '1' by writing 9 bytes into address '0'?

Alternatively, if it was really a 24-bit address field, with each address being a 16-byte/128-bit block, that would seem like a simpler explanation, if maybe the part interface is shared with a 512MB module and the MSB is unused in the Au's part.
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#2
So the data bus is only 16 bits wide but the DDR3 controller always operates in bursts of 8 so you end up with the last three address bits being 0 and reading/writing in 128 bit chunks. This is a design choice of the controller and not a restriction of the DDR3 itself.

This means each of the addresses excluding the last three bits are 16 bytes wide. This gives you 2^24 addresses as you pointed out. The MSB is always 0 since it corresponds to the "bank" which is used when you have multiple DDR3 chips.
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