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DDR3 speed of READ command
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I try to use DDR3 memory on the Au board for my project and it looks like the first read data get from the FSM I got after about 270nS. It related to about 22 cycles  of  ui_clk. Is it normal behave of DDR3 or have something wrong, please? I need accidently access to memory addresses  for reading and writing by CPU without postponing of reading. Write is no critical because FIFO can be use, but read have to be fast (50ns is enough). Thanks for help.
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