I’m trying to work through the Learning FPGAs book with my Cu using Labs 2.0.8, and this code fails to build:
module alchitryTop (
input clk, // 100MHz clock
input rst_n, // reset button (active low)
output led[8], // 8 user controllable LEDs
input usbRx, // USB->Serial input
output usbTx, // USB->Serial output
output ioLed[3][8], // LEDs on IO Shield
output ioSeg[8], // 7-segment LEDs on IO Shield
output ioSel[4], // Digit select on IO Shield
input ioButton[5], // 5 buttons on IO Shield
input ioDip[3][8] // DIP switches on IO Shield
) {
sig rst // reset signal
.clk(clk) {
// The reset conditioner is used to synchronize the reset signal to the FPGA
// clock. This ensures the entire FPGA comes out of reset at the same time.
resetConditioner resetCond
}
decoder dec(#WIDTH(3))
encoder enc(#WIDTH(8))
arbiter arb(#WIDTH(8))
always {
resetCond.in = ~rst_n // input raw inverted reset signal
rst = resetCond.out // conditioned reset
led = 8h00 // turn LEDs off
usbTx = usbRx // loop serial port
ioLed = 3x{{8h00}}
ioSeg = 8hFF //turn segments off
ioSel = 4hF //select no digits
dec.in = ioDip[0][2:0]
enc.in = ioDip[1]
arb.in = ioDip[2]
ioLed[0] = dec.out
ioLed[1] = enc.out
ioLed[2] = arb.out
}
}
IDE doesn’t tell me that anything is wrong with it. Here is the error I get:
Failed to convert source files to Verilog. This should be considered a bug!
Error at line 45 offset 15: Failed to resolve signal for "i"
java.lang.IllegalStateException: Error at line 45 offset 15: Failed to resolve signal for "i"
Along with a bunch of kotlin errors. Is there a simple fix in my code I’m not seeing? Or is there a bug in Alchitry labs?