I just picked up an Alchitry Au, and also an Ft. I have the Ft demo (pulled from this forum) working, and I can see the output with one of FTDI’s demo apps, so it’s all working. However, the data rate I’m seeing is only 51MB/sec instead of the advertised 200MB/sec. I am using a USB cable which is rated to 10Gbit, and the USB ports on my machine are also rated for SuperSpeed.
Any guesses on what might be still wrong? 51MB/sec feels very suspiciously like it’s really still only managing to run at 480Mbit level USB, but I don’t know where the bottleneck might be.
I should note that this is not blocking me on my project at all, the available bandwidth I’m already getting is a comfortable multiple of my initial use case needs. Eventually though, I am likely to want to take it all the way as far as it can go.
Answering the question myself- there’s a timer with period 5 in the example design, which is deliberately throttling the rate at which it feeds data into the pipe. When I reduced that period to 1, the throughput went up to 127 MB/sec. Removing the idle timer entirely would require refactoring the example a bit, which I don’t feel like attempting yet. But I’m satisfied that I understand it enough now!
The Ft should be able to get very close to the 200MB/s bandwidth. I was hitting upper 190s on my desktop.
There is some overhead IIRC when switching between reads/writes so the bidirectional bandwidth is a little lower than using it all for just dumping data.
Yeah, I can see how the theo max lines up pretty closely with writing 16 bits to the FT600 at 100Mhz. The USB3 capacity is 5Gbit or more, so the bottleneck is clearly delivering to the chip.
I had a different issue where the last 16 bits of all of my transfers was getting dropped, and it was due to the example FT reference code on the forum didn’t make it clear that you need to keep WR enabled until the cycle after you latch your last 16 bit transfer. I figured this out by looking at the FT600 datasheet and noticing it in the timing diagram.
Overall I am super pleased by the board so far. It took me less than a week to get my project delivering the entire Apple II bus capture over USB to a Raspberry Pi5. And I’ve never done any FPGA development before!
I can tell that Lucid is hiding a lot of details from me but I don’t mind yet. It is working as excellent training wheels for the moment.