As I understand your question, there are two ways to do what you want:
Work entirely in Vivado to build the project, then use the Alchitry loader to download it to the board (since the Au is not recognized by the Vivado hardware manager). You can find the Alchitry loader here: https://alchitry.com/pages/alchitry-loader
Build your core using the “Wizard” in Vivado, then import the resulting files into your Alchitry labs project. I haven’t done this with CORE, but I have an example using the XADC wizard here: https://eprebys.faculty.ucdavis.edu/alchitry-notes/
Note that Vivado doesn’t support Lucid, so if you want to write in Lucid, you need option 2.
Is it possible to make and then use board files for the Alchitry Au for Vivado? There was an attempt here: https://forum.alchitry.com/thread-69.html though the original poster never commented back about their experience with it.
Why is the Alchitry Au not recognized by the Vivado hardware manager?
I haven’t personally used the board files. As for why this board doesn’t work with the Hardware Manager, you’ll have to ask the Alchitry people about that.
For the record, I’ve found their loader much more robust than the Xilinx Hardware Manager. I used to use an officially supported Digilent board for an electronics class I teach, and the hardware manager was an endless headache. It would frequently just stop working for no apparent reason, and we’d have to uninstall and reinstall the drivers. It also had a lot of problems working from the Windows VM on my Mac. We switched to this board with their loader, and so far there are no problems.
PWM works great.
To make the PWM wave in the Au using Verilog.
Follow the online tutorial at https://alchitry.com/blogs/tutorials/pulse-width-modulation
and copy the led_wave.v module from the tutorial as a new Verilog Source in Alchitry Labs.
Modify the au_top.v to instantiate the led_wave module and build the project.
(Note: I added the Io’s io_leds to a new Constrainsts file called io_led.acf)
// The reset conditioner is used to synchronize the reset signal to the FPGA
// clock. This ensures the entire FPGA comes out of reset at the same time.
reset_conditioner reset_conditioner(
.clk(clk),
.in(!rst_n),
.out(rst)
);