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Alchitry Au+ / ft600
Good afternoon,
I'm trying to connect my FPGA Au+ with the module Alchitry ft600 but there is a problem that I cannot resolve. My code must be write in VHDL and not in Lucid or Verilog. I red yours tutorial and downloaded the Lucid File but I don't know how to report this in VHDL language.
I hope that you response me as soon as possible.

Thanks at all, 

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