quad spi flash, E8, qspi_flash_sck_io

[sumbals]

I'm trying to get the Quad SPI flash to work with the Microblaze IP. (based on https://www.fpgadeveloper.com/2017/11/ar...ject.html/)

Vivado complains about a pin not being connected namely 'qspi_flash_sck_io'. This pin is connected to E8 but I can not select E8 in the package pin.
All the other qpsi_flash pins (J13, J14, K15, K16, L12) are available but not for the qspi_flash_sck_io...
I assume this has something to do with the fact that all the other pins are of IO/TYPE - HR, while the E8 is of IO/TYPE CONFIG (https://www.xilinx.com/content/dam/xilin...256pkg.txt)

Notice that I'm using the board files provided by seware74 (https://forum.alchitry.com/thread-69.html)

How can I correctly configure the Quad SPI flash?

[sumbals]

I'm trying to get the Quad SPI flash to work with the Microblaze IP. (based on https://www.fpgadeveloper.com/2017/11/ar...ject.html/)

Vivado complains about a pin not being connected namely 'qspi_flash_sck_io'. This pin is connected to E8 but I can not select E8 in the package pin.
All the other qpsi_flash pins (J13, J14, K15, K16, L12) are available but not for the qspi_flash_sck_io...
I assume this has something to do with the fact that all the other pins are of IO/TYPE - HR, while the E8 is of IO/TYPE CONFIG (https://www.xilinx.com/content/dam/xilin...256pkg.txt)

Notice that I'm using the board files provided by seware74 (https://forum.alchitry.com/thread-69.html)

How can I correctly configure the Quad SPI flash?

I've noticed that when you enable the 'Enable STARTUP Primitive' option within the quad spi block, the qspi_flash_sck_io is not presented in the 'I/O ports' and fixed the problem.
I'm now able to generate a bitstream with the Quad SPI IP.