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JTAG and QSPI Flash on Alchitry Au

I'm working on a soft-core CPU design on the Alchitry Au. Ideally, I would like to use the JTAG interface from the FTDI chip to debug and program my cpu with GDB. It looks like I can make use of the BSCANE2 primitive referenced on page 175 of the 7 series FPGA user guide. However, the only example I've found of this primitive being used with the Alchitry Au is in the au-bridge git project, which seems to be undocumented. I want to check making use of this doesn't interfere with how the Alchitry loader writes the bitstream.

Additionally, it would also be nice to have some non-volatile memory to store the CPU's program in. From looking at the schematic, it looks like the on board QSPI flash is used to store the bitstream to initialise the FPGA. But the au-bridge project seems to allow programming this flash, so I would like to know if any of this can be used for user data, or if I would need my own flash chip for this.

Thanks for the help,
Hi Charlie,

I have much the same topic:

I made a design in Vivado and programmed my microblaze with Vitis.
I connected the plattform cable via Br-Board direct to the JTAG pins.
Therefore i can upload my design and use all online debugging tools
provided by Vintis.

However, I found no way to store the design and the program in the spi flash.

The used SPI Flash (Microchip SST26VF032B) is not supported by Vivado.
So I can't use "add Configuration Memory Device" in Vivados Hardware Manager.

On the other hand I don't know how to integrate the programm into the bitstream.
With makes the alchtry loader useless to me.

Does anybody know, how to bring the design and the program into the spi flash?

Thank you,
The source code for the command-line loader is directly available at: https://github.com/alchitry/alchitry-loader.
It uses lib USB as a static library in the repo, but you can get the API and source for that too. From there you could see how the loader writes and use a modified version to write your program at the appropriate address above the configuration. A little SPI loader in your FPGA design to pull the instructions over into whatever you are using for memory or cache and you're golden.

Sorry if that's not what you want but it's the only path I can see. Perhaps someone wiser will be able to suggest something else.

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